Merge branch 'master' of git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / keystone / init.c

diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index 4df5ae1cae97f75cc0b5609888b982a66b396c22..c2b947839d292a14090e15d951703eb99e517f6e 100644 (file)
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -10,25 +10,78 @@
 #include <common.h>
 #include <ns16550.h>
 #include <asm/io.h>
+#include <asm/arch/msmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/psc_defs.h>
 
 void chip_configuration_unlock(void)
 {
-       __raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
-       __raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
+       __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
+       __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
 }
 
+#ifdef CONFIG_SOC_K2L
+void osr_init(void)
+{
+       u32 i;
+       u32 j;
+       u32 val;
+       u32 base = KS2_OSR_CFG_BASE;
+       u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
+
+       /* Enable the OSR clock domain */
+       psc_enable_module(KS2_LPSC_OSR);
+
+       /* Disable OSR ECC check for all the ram banks */
+       for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
+               val = i | KS2_OSR_ECC_VEC_TRIG_RD |
+                       (KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
+
+               writel(val , base + KS2_OSR_ECC_VEC);
+
+               /**
+                * wait till read is done.
+                * Print should be added after earlyprintk support is added.
+                */
+               for (j = 0; j < 10000; j++) {
+                       val = readl(base + KS2_OSR_ECC_VEC);
+                       if (val & KS2_OSR_ECC_VEC_RD_DONE)
+                               break;
+               }
+
+               ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
+                                               KS2_OSR_ECC_CTRL_CHK;
+
+               writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
+               writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
+       }
+
+       /* Reset OSR memory to all zeros */
+       for (i = 0; i < KS2_OSR_SIZE; i += 4)
+               writel(0, KS2_OSR_DATA_BASE + i);
+
+       /* Enable OSR ECC check for all the ram banks */
+       for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
+               writel(ecc_ctrl[i] |
+                      KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
+}
+#endif
+
 int arch_cpu_init(void)
 {
        chip_configuration_unlock();
        icache_enable();
 
-#ifdef CONFIG_SOC_K2HK
-       share_all_segments(8);
-       share_all_segments(9);
-       share_all_segments(10); /* QM PDSP */
-       share_all_segments(11); /* PCIE */
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
+       msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
+#endif
+#ifdef CONFIG_SOC_K2L
+       osr_init();
 #endif
 
        /*