mx51: Fix USB PHY clocks

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx5 / clock.c

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 171d7629ef17e96cdc5e16f2bc7f663df34a342b..4e10d81c9820b0be1447e4d7aa078b8e7370cfb6 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -126,23 +126,33 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 }
 #endif
 
-void set_usb_phy1_clk(void)
+void set_usb_phy_clk(void)
 {
        clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
+#if defined(CONFIG_MX51)
 void enable_usb_phy1_clk(unsigned char enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
-       clrsetbits_le32(&mxc_ccm->CCGR4,
-                       MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
-                       MXC_CCM_CCGR4_USB_PHY1(cg));
+       clrsetbits_le32(&mxc_ccm->CCGR2,
+                       MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+                       MXC_CCM_CCGR2_USB_PHY(cg));
 }
 
-void set_usb_phy2_clk(void)
+void enable_usb_phy2_clk(unsigned char enable)
 {
-       clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
+       /* i.MX51 has a single USB PHY clock, so do nothing here. */
+}
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(unsigned char enable)
+{
+       unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+       clrsetbits_le32(&mxc_ccm->CCGR4,
+                       MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
+                       MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
 void enable_usb_phy2_clk(unsigned char enable)
@@ -153,6 +163,7 @@ void enable_usb_phy2_clk(unsigned char enable)
                        MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
                        MXC_CCM_CCGR4_USB_PHY2(cg));
 }
+#endif
 
 /*
  * Calculate the frequency of PLLn.
@@ -804,7 +815,7 @@ void mxc_set_sata_internal_clock(void)
        u32 *tmp_base =
                (u32 *)(IIM_BASE_ADDR + 0x180c);
 
-       set_usb_phy1_clk();
+       set_usb_phy_clk();
 
        clrsetbits_le32(tmp_base, 0x6, 0x4);
 }