Merge 'u-boot-microblaze/zynq' into (u-boot-arm/master'

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / mx5 / clock.c

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index a59b88a490b74009720c2bc91881317432b01448..6bef2544564a6e2924ee11426432453f623e0baf 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -4,23 +4,7 @@
  *
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -101,7 +85,7 @@ void set_usboh3_clk(void)
                        MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
 }
 
-void enable_usboh3_clk(unsigned char enable)
+void enable_usboh3_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -111,12 +95,16 @@ void enable_usboh3_clk(unsigned char enable)
 }
 
 #ifdef CONFIG_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
        u32 mask;
 
+#if defined(CONFIG_MX51)
+       if (i2c_num > 1)
+#elif defined(CONFIG_MX53)
        if (i2c_num > 2)
+#endif
                return -EINVAL;
        mask = MXC_CCM_CCGR_CG_MASK <<
                        (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
@@ -134,7 +122,7 @@ void set_usb_phy_clk(void)
 }
 
 #if defined(CONFIG_MX51)
-void enable_usb_phy1_clk(unsigned char enable)
+void enable_usb_phy1_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -143,12 +131,12 @@ void enable_usb_phy1_clk(unsigned char enable)
                        MXC_CCM_CCGR2_USB_PHY(cg));
 }
 
-void enable_usb_phy2_clk(unsigned char enable)
+void enable_usb_phy2_clk(bool enable)
 {
        /* i.MX51 has a single USB PHY clock, so do nothing here. */
 }
 #elif defined(CONFIG_MX53)
-void enable_usb_phy1_clk(unsigned char enable)
+void enable_usb_phy1_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -157,7 +145,7 @@ void enable_usb_phy1_clk(unsigned char enable)
                        MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
-void enable_usb_phy2_clk(unsigned char enable)
+void enable_usb_phy2_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -334,7 +322,7 @@ static u32 get_ipg_per_clk(void)
 /* Get the output clock rate of a standard PLL MUX for peripherals. */
 static u32 get_standard_pll_sel_clk(u32 clk_sel)
 {
-       u32 freq;
+       u32 freq = 0;
 
        switch (clk_sel & 0x3) {
        case 0:
@@ -390,6 +378,44 @@ static u32 imx_get_cspiclk(void)
        return ret_val;
 }
 
+/*
+ * get esdhc clock rate.
+ */
+static u32 get_esdhc_clk(u32 port)
+{
+       u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
+       u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+       u32 cscdr1 = readl(&mxc_ccm->cscdr1);
+
+       switch (port) {
+       case 0:
+               clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
+               pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
+               podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
+               break;
+       case 1:
+               clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
+               pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
+               podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
+               break;
+       case 2:
+               if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
+                       return get_esdhc_clk(1);
+               else
+                       return get_esdhc_clk(0);
+       case 3:
+               if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
+                       return get_esdhc_clk(1);
+               else
+                       return get_esdhc_clk(0);
+       default:
+               break;
+       }
+
+       freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
+       return freq;
+}
+
 static u32 get_axi_a_clk(void)
 {
        u32 cbcdr = readl(&mxc_ccm->cbcdr);
@@ -473,6 +499,14 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
                return get_uart_clk();
        case MXC_CSPI_CLK:
                return imx_get_cspiclk();
+       case MXC_ESDHC_CLK:
+               return get_esdhc_clk(0);
+       case MXC_ESDHC2_CLK:
+               return get_esdhc_clk(1);
+       case MXC_ESDHC3_CLK:
+               return get_esdhc_clk(2);
+       case MXC_ESDHC4_CLK:
+               return get_esdhc_clk(3);
        case MXC_FEC_CLK:
                return get_ipg_clk();
        case MXC_SATA_CLK:
@@ -689,10 +723,11 @@ static int config_core_clk(u32 ref, u32 freq)
 static int config_nfc_clk(u32 nfc_clk)
 {
        u32 parent_rate = get_emi_slow_clk();
-       u32 div = parent_rate / nfc_clk;
+       u32 div;
 
-       if (nfc_clk <= 0)
+       if (nfc_clk == 0)
                return -EINVAL;
+       div = parent_rate / nfc_clk;
        if (div == 0)
                div++;
        if (parent_rate / div > NFC_CLK_MAX)
@@ -705,6 +740,15 @@ static int config_nfc_clk(u32 nfc_clk)
        return 0;
 }
 
+void enable_nfc_clk(unsigned char enable)
+{
+       unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+       clrsetbits_le32(&mxc_ccm->CCGR5,
+               MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
+               MXC_CCM_CCGR5_EMI_ENFC(cg));
+}
+
 /* Config main_bus_clock for periphs */
 static int config_periph_clk(u32 ref, u32 freq)
 {
@@ -878,7 +922,9 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
        printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
        printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-
+#ifdef CONFIG_MXC_SPI
+       printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
        return 0;
 }