struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
- if (freq < ENET_25MHz || freq > ENET_125MHz)
+ if (freq < ENET_25MHZ || freq > ENET_125MHZ)
return -EINVAL;
reg = readl(&anatop->pll_enet);
ungate_sata_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
}
+
+void disable_sata_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
+}
#endif
int enable_pcie_clock(void)
case MXC_SATA_CLK:
return get_ahb_clk();
default:
+ printf("Unsupported MXC CLK: %d\n", clk);
break;
}
- return -1;
+ return 0;
}
/*