ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / omap5 / sdram.c

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7d8cec08c2f189283e0a7e170763db98e3a5818b..61e9aefe0916e15fcb346caee8020fb5c3f22ae2 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -141,7 +141,8 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_config_init              = 0x61851ab2,
        .sdram_config                   = 0x61851ab2,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
@@ -165,7 +166,8 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_config_init              = 0x61851B32,
        .sdram_config                   = 0x61851B32,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
@@ -186,18 +188,19 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 };
 
 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
-       .sdram_config_init              = 0x61851AB2,
-       .sdram_config                   = 0x61851AB2,
+       .sdram_config_init              = 0x61862B32,
+       .sdram_config                   = 0x61862B32,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
-       .sdram_tim1                     = 0xCCCF36B3,
-       .sdram_tim2                     = 0x308F7FDA,
-       .sdram_tim3                     = 0x027F88A8,
+       .ref_ctrl                       = 0x0000493E,
+       .ref_ctrl_final                 = 0x0000144A,
+       .sdram_tim1                     = 0xD113781C,
+       .sdram_tim2                     = 0x308F7FE3,
+       .sdram_tim3                     = 0x009F86A8,
        .read_idle_ctrl                 = 0x00050000,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
-       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_phy_ctlr_1_init       = 0x0E24400D,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400D,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
        .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
        .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,