struct fel_stash {
uint32_t sp;
uint32_t lr;
+ uint32_t cpsr;
+ uint32_t sctlr;
+ uint32_t vbar;
+ uint32_t cr;
};
struct fel_stash fel_stash __attribute__((section(".data")));
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
- sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
+#if defined(CONFIG_MACH_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
+#else
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
+#endif
sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
- sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
- sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
- sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
- sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
void s_init(void)
{
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
/* Magic (undocmented) value taken from boot0, without this DRAM
* access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#endif
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
- defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
+#if defined CONFIG_MACH_SUN6I || \
+ defined CONFIG_MACH_SUN7I || \
+ defined CONFIG_MACH_SUN8I
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
*/
u32 spl_boot_device(void)
{
+#ifdef CONFIG_SPL_FEL
+ /*
+ * This is the legacy compile time configuration for a special FEL
+ * enabled build. It has many restrictions and can only boot over USB.
+ */
+ return BOOT_DEVICE_BOARD;
+#else
/*
- * Have we been asked to return to the FEL portion of the boot ROM?
- * TODO: We need a more robust test here, or bracket this with
- * #ifdef CONFIG_SPL_FEL.
+ * When booting from the SD card, the "eGON.BT0" signature is expected
+ * to be found in memory at the address 0x0004 (see the "mksunxiboot"
+ * tool, which generates this header).
+ *
+ * When booting in the FEL mode over USB, this signature is patched in
+ * memory and replaced with something else by the 'fel' tool. This other
+ * signature is selected in such a way, that it can't be present in a
+ * valid bootable SD card image (because the BROM would refuse to
+ * execute the SPL in this case).
+ *
+ * This branch is just making a decision at runtime whether to load
+ * the main u-boot binary from the SD card (if the "eGON.BT0" signature
+ * is found) or return to the FEL code in the BROM to wait and receive
+ * the main u-boot binary over USB.
*/
- if (fel_stash.lr >= 0xffff0000 && fel_stash.lr < 0xffff4000)
+ if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
+ return BOOT_DEVICE_MMC1;
+ else
return BOOT_DEVICE_BOARD;
-
- return BOOT_DEVICE_MMC1;
+#endif
}
/* No confirmation data available in SPL yet. Hardcode bootmode */
void reset_cpu(ulong addr)
{
-#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+#ifdef CONFIG_SUNXI_GEN_SUN4I
static const struct sunxi_wdog *wdog =
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
-#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
+#endif
+#ifdef CONFIG_SUNXI_GEN_SUN6I
static const struct sunxi_wdog *wdog =
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;