Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800

[karo-tx-uboot.git] / arch / arm / cpu / armv7 / uniphier / ph1-ld4 / pll_init.c

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
index 68b9d5ff2798d4e9210ec1313c9ea94dd08c8f3d..b83582fee798b5677088caf2f312d1a0ffc94e5f 100644 (file)
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
@@ -11,7 +11,7 @@
 
 #undef DPLL_SSC_RATE_1PER
 
-void dpll_init(void)
+static void dpll_init(void)
 {
        u32 tmp;
 
@@ -42,7 +42,7 @@ void dpll_init(void)
        writel(tmp, SC_DPLLCTRL2);
 }
 
-void upll_init(void)
+static void upll_init(void)
 {
        u32 tmp, clk_mode_upll, clk_mode_axosel;
 
@@ -82,7 +82,7 @@ void upll_init(void)
        writel(tmp, SC_UPLLCTRL);
 }
 
-void vpll_init(void)
+static void vpll_init(void)
 {
        u32 tmp, clk_mode_axosel;