#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES2_BASE 0x02324000
+#define KS2_LANES_PER_SGMII_SERDES 4
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 1
#define KS2_NETCP_PDMA_SCHED_BASE 0x24186100
#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000
#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
-#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
-#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
#define KS2_NETCP_PDMA_TX_SND_QUEUE 896
+/* NETCP */
+#define KS2_NETCP_BASE 0x24000000
+
#endif