* Copyright (C) 2009 Ilya Yanok,
* Emcraft Systems <yanok@emcraft.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _IMX_REGS_H
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
-#ifdef CONFIG_FEC_MXC
-extern void mx25_fec_init_pins(void);
-#endif
-
/* Clock Control Module (CCM) registers */
struct ccm_regs {
u32 mpctl; /* Core PLL Control */
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
- u32 res1[0x1f5];
+ u32 iim_prg_p;
+ u32 iim_scs0;
+ u32 iim_scs1;
+ u32 iim_scs2;
+ u32 iim_scs3;
+ u32 res1[0x1f1];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
};
struct fuse_bank0_regs {
- u32 fuse0_25[0x1a];
+ u32 fuse0_7[8];
+ u32 uid[8];
+ u32 fuse16_25[0xa];
u32 mac_addr[6];
};
+struct fuse_bank1_regs {
+ u32 fuse0_21[0x16];
+ u32 usr5;
+ u32 fuse23_29[7];
+ u32 usr6[2];
+};
+
/* Multi-Layer AHB Crossbar Switch (MAX) registers */
struct max_regs {
u32 mpr0;
#define IMX_CSPI1_BASE (0x43FA4000)
#define IMX_KPP_BASE (0x43FA8000)
#define IMX_IOPADMUX_BASE (0x43FAC000)
+#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE
#define IMX_IOPADCTL_BASE (0x43FAC22C)
#define IMX_IOPADGRPCTL_BASE (0x43FAC418)
#define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
#define IMX_PWM1_BASE (0x53FE0000)
#define IMX_RTIC_BASE (0x53FEC000)
#define IMX_IIM_BASE (0x53FF0000)
+#define IIM_BASE_ADDR IMX_IIM_BASE
#define IMX_USB_BASE (0x53FF4000)
+#define IMX_USB_PORT_OFFSET 0x200
#define IMX_CSI_BASE (0x53FF8000)
#define IMX_DRYICE_BASE (0x53FFC000)