OMAP3: Suffix all Micron memory timing parts with their speed

[karo-tx-uboot.git] / arch / arm / include / asm / arch-omap3 / mem.h

diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index db6a696f49c2b51f2d740978281f3dce093a106a..4f996d9eb3b6ca1f7865fadf9b6926e83edd70f6 100644 (file)
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -39,10 +39,26 @@ enum {
 
 #define EARLY_INIT     1
 
+/*
+ * For a full explanation of these registers and values please see
+ * the Technical Reference Manual (TRM) for any of the processors in
+ * this family.
+ */
+
 /* Slower full frequency range default timings for x32 operation*/
 #define SDRC_SHARING   0x00000100
 #define SDRC_MR_0_SDR  0x00000031
 
+/*
+ * SDRC autorefresh control values.  This register consists of autorefresh
+ * enable at bits 0:1 and an autorefresh counter value in bits 8:23.  The
+ * counter is a result of ( tREFI / tCK ) - 50.
+ */
+#define SDP_3430_SDRC_RFR_CTRL_100MHz  0x0002da01
+#define SDP_3430_SDRC_RFR_CTRL_133MHz  0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
+#define SDP_3430_SDRC_RFR_CTRL_165MHz  0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
+#define SDP_3430_SDRC_RFR_CTRL_200MHz  0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
+
 #define DLL_OFFSET             0
 #define DLL_WRITEDDRCLKX2DIS   1
 #define DLL_ENADLL             1
@@ -86,6 +102,27 @@ enum {
                ACTIM_CTRLB_TXP(b)      |       \
                ACTIM_CTRLB_TXSR(d)
 
+/*
+ * Values used in the MCFG register.  Only values we use today
+ * are defined and the rest can be found in the TRM.  Unless otherwise
+ * noted all fields are one bit.
+ */
+#define V_MCFG_RAMTYPE_DDR             (0x1)
+#define V_MCFG_DEEPPD_EN               (0x1 << 3)
+#define V_MCFG_B32NOT16_32             (0x1 << 4)
+#define V_MCFG_BANKALLOCATION_RBC      (0x2 << 6)      /* 6:7 */
+#define V_MCFG_RAMSIZE(a)              ((((a)/(1024*1024))/2) << 8) /* 8:17 */
+#define V_MCFG_ADDRMUXLEGACY_FLEX      (0x1 << 19)
+#define V_MCFG_CASWIDTH_10B            (0x5 << 20)     /* 20:22 */
+#define V_MCFG_RASWIDTH(a)             ((a) << 24)     /* 24:26 */
+
+/* Macro to construct MCFG */
+#define MCFG(a, b)                                             \
+               V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B |      \
+               V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) | \
+               V_MCFG_BANKALLOCATION_RBC |                     \
+               V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
+
 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
 #define INFINEON_TDAL_165      6       /* Twr/Tck + Trp/tck            */
                                        /* 15/6 + 18/6 = 5.5 -> 6       */
@@ -138,32 +175,16 @@ enum {
                ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165,   \
                                MICRON_TXP_165, MICRON_XSR_165)
 
-#define MICRON_RAMTYPE                 0x1
-#define MICRON_DDRTYPE                 0x0
-#define MICRON_DEEPPD                  0x1
-#define MICRON_B32NOT16                        0x1
-#define MICRON_BANKALLOCATION  0x2
-#define MICRON_RAMSIZE                 ((PHYS_SDRAM_1_SIZE/(1024*1024))/2)
-#define MICRON_ADDRMUXLEGACY   0x1
-#define MICRON_CASWIDTH                        0x5
-#define MICRON_RASWIDTH                        0x2
-#define MICRON_LOCKSTATUS              0x0
-#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \
-       (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \
-       (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \
-       (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \
-       (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
-
-#define MICRON_ARCV                            2030
-#define MICRON_ARE                             0x1
-#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE))
-
-#define MICRON_BL                              0x2
-#define MICRON_SIL                             0x0
-#define MICRON_CASL                            0x3
-#define MICRON_WBST                            0x0
-#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \
-       (MICRON_SIL << 3) | (MICRON_BL))
+#define MICRON_RASWIDTH_165    0x2
+#define MICRON_V_MCFG_165(size)        MCFG((size), MICRON_RASWIDTH_165)
+
+#define MICRON_BL_165                  0x2
+#define MICRON_SIL_165                 0x0
+#define MICRON_CASL_165                        0x3
+#define MICRON_WBST_165                        0x0
+#define MICRON_V_MR_165                        ((MICRON_WBST_165 << 9) | \
+               (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
+               (MICRON_BL_165))
 
 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
 #define NUMONYX_TDAL_165       6       /* Twr/Tck + Trp/tck            */
@@ -199,9 +220,9 @@ enum {
 #ifdef CONFIG_OMAP3_MICRON_DDR
 #define V_ACTIMA_165           MICRON_V_ACTIMA_165
 #define V_ACTIMB_165           MICRON_V_ACTIMB_165
-#define V_MCFG                 MICRON_V_MCFG
-#define V_RFR_CTRL             MICRON_V_RFR_CTRL
-#define V_MR                   MICRON_V_MR
+#define V_MCFG                 MICRON_V_MCFG_165(PHYS_SDRAM_1_SIZE)
+#define V_RFR_CTRL             SDP_3430_SDRC_RFR_CTRL_165MHz
+#define V_MR                   MICRON_V_MR_165
 #endif
 
 #ifdef CONFIG_OMAP3_NUMONYX_DDR
@@ -259,6 +280,10 @@ enum {
 #define GPMC_SIZE_32M  0xE
 #define GPMC_SIZE_16M  0xF
 
+#define GPMC_BASEADDR_MASK     0x3F
+
+#define GPMC_CS_ENABLE         0x1
+
 #define SMNAND_GPMC_CONFIG1    0x00000800
 #define SMNAND_GPMC_CONFIG2    0x00141400
 #define SMNAND_GPMC_CONFIG3    0x00141400