ARM: OMAP5: Correct the DRAM_ADDR_SPACE_END macro.

[karo-tx-uboot.git] / arch / arm / include / asm / arch-omap5 / omap.h

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 7e17c76166274a5a62cd1a3618558f74c9a5c928..2961c6b5fa8d950a2f6298f05b11def999d14139 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -40,7 +40,7 @@
 #define OMAP54XX_L4_PER_BASE   0x48000000
 
 #define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
-#define OMAP54XX_DRAM_ADDR_SPACE_END   0xD0000000
+#define OMAP54XX_DRAM_ADDR_SPACE_END   0xFFFFFFFF
 #define DRAM_ADDR_SPACE_START  OMAP54XX_DRAM_ADDR_SPACE_START
 #define DRAM_ADDR_SPACE_END    OMAP54XX_DRAM_ADDR_SPACE_END
 
@@ -98,17 +98,6 @@
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
 
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE               0x4AE06000
-#define PRM_DEVICE_BASE                (PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL            PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET      0x01
-
 /* Control Module */
 #define LDOSRAM_ACTMODE_VSET_IN_MASK   (0x1F << 5)
 #define LDOSRAM_VOLT_CTRL_OVERRIDE     0x0401040f
@@ -125,9 +114,10 @@
 /* CONTROL_EFUSE_2 */
 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1           0x00ffc000
 
-#define MMC1_PWRDNZ                                    (1 << 26)
-#define MMC1_PBIASLITE_PWRDNZ                          (1 << 22)
-#define MMC1_PBIASLITE_VMODE                           (1 << 21)
+#define SDCARD_PWRDNZ                                  (1 << 26)
+#define SDCARD_BIAS_HIZ_MODE                           (1 << 25)
+#define SDCARD_BIAS_PWRDNZ                             (1 << 22)
+#define SDCARD_PBIASLITE_VMODE                         (1 << 21)
 
 #ifndef __ASSEMBLY__
 
@@ -136,6 +126,10 @@ struct s32ktimer {
        unsigned int s32k_cr;   /* 0x10 */
 };
 
+#define DEVICE_TYPE_SHIFT 0x6
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+#define DEVICE_GP 0x3
+
 struct omap_sys_ctrl_regs {
        u32 pad0[77]; /* 0x4A002000 */
        u32 control_status; /* 0x4A002134 */