#define __ASM_ARCH_RCAR_BASE_H
/*
- * R-Car (R8A7790/R8A7791) I/O Addresses
+ * R-Car (R8A7790/R8A7791/R8A7794) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define GPIO5_BASE 0xE6055000
#define SH_QSPI_BASE 0xE6B10000
+/* SCIF */
+#define SCIF0_BASE 0xE6E60000
+#define SCIF1_BASE 0xE6E68000
+#define SCIF2_BASE 0xE6E58000
+#define SCIF3_BASE 0xE6EA8000
+#define SCIF4_BASE 0xE6EE0000
+#define SCIF5_BASE 0xE6EE8000
+
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00
#define SYS_AXI_SAT1_BASE 0xFF8009C0
#define SYS_AXI_SDM0_BASE 0xFF800A00
#define SYS_AXI_SDM1_BASE 0xFF800A40
-#define SYS_AXI_TRAB_BASE 0xFF800B00
+#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
#define SYS_AXI_UDM0_BASE 0xFF800B80
#define SYS_AXI_UDM1_BASE 0xFF800BC0
#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
#define CCI_AXI_AX2ADDRMASK 0xFF88041C
+#define PLL0CR 0xE61500D8
+#define PLL0_STC_MASK 0x7F000000
+#define PLL0_STC_BIT 24
+#define PLLECR 0xE61500D0
+#define PLL0ST 0x100
+
#ifndef __ASSEMBLY__
#include <asm/types.h>
u32 s3cexclidmsk;
u32 s3cadsplcr;
u32 s3cmaar;
- u32 s3carcr11; /* R8a7790 only */
+ u32 s3carcr11;
u32 s3crorr;
u32 s3cworr;
u32 s3carcr22;