#define __ASM_ARCH_RCAR_BASE_H
/*
- * R-Car (R8A7790/R8A7791) I/O Addresses
+ * R-Car (R8A7790/R8A7791/R8A7793/R8A7794) I/O Addresses
*/
#define RWDT_BASE 0xE6020000
#define SWDT_BASE 0xE6030000
#define SCIF4_BASE 0xE6EE0000
#define SCIF5_BASE 0xE6EE8000
+/*
+ * SH-I2C
+ * Ch2 and ch3 are different address. These are defined
+ * in the header of each SoCs.
+ */
+#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000
+#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000
+
+/* RCAR-I2C */
+#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000
+#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000
+#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000
+#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000
+
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00
#define SYS_AXI_SAT1_BASE 0xFF8009C0
#define SYS_AXI_SDM0_BASE 0xFF800A00
#define SYS_AXI_SDM1_BASE 0xFF800A40
-#define SYS_AXI_TRAB_BASE 0xFF800B00
+#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
#define SYS_AXI_UDM0_BASE 0xFF800B80
#define SYS_AXI_UDM1_BASE 0xFF800BC0
#define PLL0CR 0xE61500D8
#define PLL0_STC_MASK 0x7F000000
#define PLL0_STC_BIT 24
+#define PLLECR 0xE61500D0
+#define PLL0ST 0x100
#ifndef __ASSEMBLY__
#include <asm/types.h>