arm: vf610: add uart0 clock/iomux definitions

[karo-tx-uboot.git] / arch / arm / include / asm / arch-vf610 / crm_regs.h

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index e3f703dc832da925ed9516fd64d004baa875d28a..04cc5bc47480130bf1aee9588f3367c11dce48e1 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -1,20 +1,7 @@
 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
@@ -68,57 +55,59 @@ struct ccm_reg {
 
 /* Analog components control digital interface (ANADIG) */
 struct anadig_reg {
+       u32 reserved_0x000[4];
        u32 pll3_ctrl;
-       u32 resv0[3];
+       u32 reserved_0x014[3];
        u32 pll7_ctrl;
-       u32 resv1[3];
+       u32 reserved_0x024[3];
        u32 pll2_ctrl;
-       u32 resv2[3];
+       u32 reserved_0x034[3];
        u32 pll2_ss;
-       u32 resv3[3];
+       u32 reserved_0x044[3];
        u32 pll2_num;
-       u32 resv4[3];
+       u32 reserved_0x054[3];
        u32 pll2_denom;
-       u32 resv5[3];
+       u32 reserved_0x064[3];
        u32 pll4_ctrl;
-       u32 resv6[3];
+       u32 reserved_0x074[3];
        u32 pll4_num;
-       u32 resv7[3];
+       u32 reserved_0x084[3];
        u32 pll4_denom;
+       u32 reserved_0x094[3];
        u32 pll6_ctrl;
-       u32 resv8[3];
+       u32 reserved_0x0A4[3];
        u32 pll6_num;
-       u32 resv9[3];
+       u32 reserved_0x0B4[3];
        u32 pll6_denom;
-       u32 resv10[3];
+       u32 reserved_0x0C4[7];
        u32 pll5_ctrl;
-       u32 resv11[3];
+       u32 reserved_0x0E4[3];
        u32 pll3_pfd;
-       u32 resv12[3];
+       u32 reserved_0x0F4[3];
        u32 pll2_pfd;
-       u32 resv13[3];
+       u32 reserved_0x104[3];
        u32 reg_1p1;
-       u32 resv14[3];
+       u32 reserved_0x114[3];
        u32 reg_3p0;
-       u32 resv15[3];
+       u32 reserved_0x124[3];
        u32 reg_2p5;
-       u32 resv16[7];
+       u32 reserved_0x134[7];
        u32 ana_misc0;
-       u32 resv17[3];
+       u32 reserved_0x154[3];
        u32 ana_misc1;
-       u32 resv18[63];
+       u32 reserved_0x164[63];
        u32 anadig_digprog;
-       u32 resv19[3];
+       u32 reserved_0x264[3];
        u32 pll1_ctrl;
-       u32 resv20[3];
+       u32 reserved_0x274[3];
        u32 pll1_ss;
-       u32 resv21[3];
+       u32 reserved_0x284[3];
        u32 pll1_num;
-       u32 resv22[3];
+       u32 reserved_0x294[3];
        u32 pll1_denom;
-       u32 resv23[3];
+       u32 reserved_0x2A4[3];
        u32 pll1_pdf;
-       u32 resv24[3];
+       u32 reserved_0x2B4[3];
        u32 pll_lock;
 };
 #endif
@@ -177,6 +166,7 @@ struct anadig_reg {
 #define CCM_CSCMR2_RMII_CLK_SEL(v)             (((v) & 0x3) << 4)
 
 #define CCM_REG_CTRL_MASK                      0xffffffff
+#define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK              (0x3 << 16)
 #define CCM_CCGR1_PIT_CTRL_MASK                        (0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK             (0x3 << 28)
@@ -190,6 +180,7 @@ struct anadig_reg {
 #define CCM_CCGR4_WKUP_CTRL_MASK               (0x3 << 20)
 #define CCM_CCGR4_CCM_CTRL_MASK                        (0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK                        (0x3 << 24)
+#define CCM_CCGR4_I2C0_CTRL_MASK               (0x3 << 12)
 #define CCM_CCGR6_OCOTP_CTRL_MASK              (0x3 << 10)
 #define CCM_CCGR6_DDRMC_CTRL_MASK              (0x3 << 28)
 #define CCM_CCGR7_SDHC1_CTRL_MASK              (0x3 << 4)