#define ZYNQ_SERIAL_BASEADDR0 0xFF000000
#define ZYNQ_SERIAL_BASEADDR1 0xFF001000
+#define ZYNQ_SPI_BASEADDR0 0xFF040000
+#define ZYNQ_SPI_BASEADDR1 0xFF050000
+
#define ZYNQ_I2C_BASEADDR0 0xFF020000
#define ZYNQ_I2C_BASEADDR1 0xFF030000
#define EMMC_MODE 0x00000006
#define JTAG_MODE 0x00000000
+#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
+
+struct iou_slcr_regs {
+ u32 mio_pin[78];
+ u32 reserved[442];
+};
+
+#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
+
#define ZYNQMP_RPU_BASEADDR 0xFF9A0000
struct rpu_regs {