mxs_reg_32(hw_apbh_version);
};
-#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_SOC_MX6))
+#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_ARCH_MX6))
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0); /* 0x000 */
mxs_reg_32(hw_apbh_ctrl1); /* 0x010 */
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
-#elif defined(CONFIG_SOC_MX6)
+#elif defined(CONFIG_ARCH_MX6)
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
-#if defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_ARCH_MX6)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#endif