ARM: at91/at91x40: remove use of at91_sys_read/write

[mv-sheeva.git] / arch / arm / mach-at91 / at91x40_time.c

diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index dfff2895f4b286c4134a2a9f6425c90ce27e76ca..6ca680a1d5d112bb32cfa347c08c845f4d24ff6f 100644 (file)
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -28,6 +28,12 @@
 #include <asm/mach/time.h>
 #include <mach/at91_tc.h>
 
+#define at91_tc_read(field) \
+       __raw_readl(AT91_TC + field)
+
+#define at91_tc_write(field, value) \
+       __raw_writel(value, AT91_TC + field);
+
 /*
  *     3 counter/timer units present.
  */
@@ -37,12 +43,12 @@
 
 static unsigned long at91x40_gettimeoffset(void)
 {
-       return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
+       return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
 }
 
 static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
 {
-       at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
+       at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
        timer_tick();
        return IRQ_HANDLED;
 }
@@ -57,20 +63,20 @@ void __init at91x40_timer_init(void)
 {
        unsigned int v;
 
-       at91_sys_write(AT91_TC + AT91_TC_BCR, 0);
-       v = at91_sys_read(AT91_TC + AT91_TC_BMR);
+       at91_tc_write(AT91_TC_BCR, 0);
+       v = at91_tc_read(AT91_TC_BMR);
        v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
-       at91_sys_write(AT91_TC + AT91_TC_BMR, v);
+       at91_tc_write(AT91_TC_BMR, v);
 
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
 
        setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
 
-       at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
+       at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
 }
 
 struct sys_timer at91x40_timer = {