if (clk == NULL || IS_ERR(clk))
return ret;
- spin_lock_irqsave(&clockfw_lock, flags);
if (clk->set_rate)
ret = clk->set_rate(clk, rate);
+
+ spin_lock_irqsave(&clockfw_lock, flags);
if (ret == 0) {
if (clk->recalc)
clk->rate = clk->recalc(clk);
{
u32 ctrl;
unsigned int locktime;
+ unsigned long flags;
if (pll->base == NULL)
return -EINVAL;
if (mult)
mult = mult - 1;
+ /* Protect against simultaneous calls to PLL setting seqeunce */
+ spin_lock_irqsave(&clockfw_lock, flags);
+
ctrl = __raw_readl(pll->base + PLLCTL);
/* Switch the PLL to bypass mode */
ctrl |= PLLCTL_PLLEN;
__raw_writel(ctrl, pll->base + PLLCTL);
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+
return 0;
}
EXPORT_SYMBOL(davinci_set_pllrate);
-int __init davinci_clk_init(struct davinci_clk *clocks)
+int __init davinci_clk_init(struct clk_lookup *clocks)
{
- struct davinci_clk *c;
+ struct clk_lookup *c;
struct clk *clk;
+ size_t num_clocks = 0;
- for (c = clocks; c->lk.clk; c++) {
- clk = c->lk.clk;
+ for (c = clocks; c->clk; c++) {
+ clk = c->clk;
if (!clk->recalc) {
if (clk->lpsc)
clk->flags |= CLK_PSC;
- clkdev_add(&c->lk);
clk_register(clk);
+ num_clocks++;
/* Turn on clocks that Linux doesn't otherwise manage */
if (clk->flags & ALWAYS_ENABLED)
clk_enable(clk);
}
+ clkdev_add_table(clocks, num_clocks);
+
return 0;
}