boot_reg = cpu_boot_reg_base();
if (soc_is_exynos4412())
boot_reg += 4*cpu;
+ else if (soc_is_exynos5420())
+ boot_reg += 4;
return boot_reg;
}
void __iomem *scu_base = scu_base_addr();
unsigned int i, ncores;
- if (soc_is_exynos5250())
- ncores = 2;
- else
+ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+ else
+ /*
+ * CPU Nodes are passed thru DT and set_cpu_possible
+ * is set by "arm_dt_init_cpu_maps".
+ */
+ return;
/* sanity check */
if (ncores > nr_cpu_ids) {