#include <asm/mach/time.h>
#include <mach/mv78xx0.h>
#include <mach/bridge-regs.h>
+#include <linux/spi/orion_spi.h>
#include <plat/cache-feroceon-l2.h>
#include <plat/ehci-orion.h>
+#include <plat/mv_xor.h>
#include <plat/orion_nand.h>
+#include <plat/orion_wdt.h>
#include <plat/time.h>
#include "common.h"
platform_device_register(&mv78xx0_ge11);
}
+/*****************************************************************************
+ * SPI
+ ****************************************************************************/
+static struct orion_spi_info mv78x00_spi_plat_data = {
+};
+
+static struct resource mv78x00_spi_resources[] = {
+ {
+ .start = SPI_PHYS_BASE,
+ .end = SPI_PHYS_BASE + SZ_512 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device mv78x00_spi = {
+ .name = "orion_spi",
+ .id = 0,
+ .resource = mv78x00_spi_resources,
+ .dev = {
+ .platform_data = &mv78x00_spi_plat_data,
+ },
+ .num_resources = ARRAY_SIZE(mv78x00_spi_resources),
+};
+
+void __init mv78x00_spi_init()
+{
+ platform_device_register(&mv78x00_spi);
+}
+
/*****************************************************************************
* I2C bus 0
****************************************************************************/
platform_device_register(&mv78xx0_uart3);
}
+/*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+
+static struct resource mv78xx0_crypto_res[] = {
+ {
+ .name = "regs",
+ .start = CRYPTO_PHYS_BASE,
+ .end = CRYPTO_PHYS_BASE + 0xffff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "sram",
+ .start = MV78XX0_SRAM_PHYS_BASE,
+ .end = MV78XX0_SRAM_PHYS_BASE + MV78XX0_SRAM_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "crypto interrupt",
+ .start = IRQ_MV78XX0_CRYPTO,
+ .end = IRQ_MV78XX0_CRYPTO,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device mv78xx0_crypto_device = {
+ .name = "mv_crypto",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(mv78xx0_crypto_res),
+ .resource = mv78xx0_crypto_res,
+};
+
+void __init mv78xx0_crypto_init(void)
+{
+ platform_device_register(&mv78xx0_crypto_device);
+}
+
+/*****************************************************************************
+ * XOR
+ ****************************************************************************/
+static struct mv_xor_platform_shared_data mv78xx0_xor_shared_data = {
+ .dram = &mv78xx0_mbus_dram_info,
+};
+
+static u64 mv78xx0_xor_dmamask = DMA_BIT_MASK(32);
+
+
+/*****************************************************************************
+ * XOR0
+ ****************************************************************************/
+static struct resource mv78xx0_xor0_shared_resources[] = {
+ {
+ .name = "xor 0 low",
+ .start = XOR0_PHYS_BASE,
+ .end = XOR0_PHYS_BASE + 0xff,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "xor 0 high",
+ .start = XOR0_HIGH_PHYS_BASE,
+ .end = XOR0_HIGH_PHYS_BASE + 0xff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device mv78xx0_xor0_shared = {
+ .name = MV_XOR_SHARED_NAME,
+ .id = 0,
+ .dev = {
+ .platform_data = &mv78xx0_xor_shared_data,
+ },
+ .num_resources = ARRAY_SIZE(mv78xx0_xor0_shared_resources),
+ .resource = mv78xx0_xor0_shared_resources,
+};
+
+static struct resource mv78xx0_xor00_resources[] = {
+ [0] = {
+ .start = IRQ_MV78XX0_XOR_0,
+ .end = IRQ_MV78XX0_XOR_0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mv_xor_platform_data mv78xx0_xor00_data = {
+ .shared = &mv78xx0_xor0_shared,
+ .hw_id = 0,
+ .pool_size = PAGE_SIZE,
+};
+
+static struct platform_device mv78xx0_xor00_channel = {
+ .name = MV_XOR_NAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mv78xx0_xor00_resources),
+ .resource = mv78xx0_xor00_resources,
+ .dev = {
+ .dma_mask = &mv78xx0_xor_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(64),
+ .platform_data = &mv78xx0_xor00_data,
+ },
+};
+
+static struct resource mv78xx0_xor01_resources[] = {
+ [0] = {
+ .start = IRQ_MV78XX0_XOR_1,
+ .end = IRQ_MV78XX0_XOR_1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mv_xor_platform_data mv78xx0_xor01_data = {
+ .shared = &mv78xx0_xor0_shared,
+ .hw_id = 1,
+ .pool_size = PAGE_SIZE,
+};
+
+static struct platform_device mv78xx0_xor01_channel = {
+ .name = MV_XOR_NAME,
+ .id = 1,
+ .num_resources = ARRAY_SIZE(mv78xx0_xor01_resources),
+ .resource = mv78xx0_xor01_resources,
+ .dev = {
+ .dma_mask = &mv78xx0_xor_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(64),
+ .platform_data = &mv78xx0_xor01_data,
+ },
+};
+
+void __init mv78xx0_xor0_init(void)
+{
+ platform_device_register(&mv78xx0_xor0_shared);
+
+ /*
+ * two engines can't do memset simultaneously, this limitation
+ * satisfied by removing memset support from one of the engines.
+ */
+ dma_cap_set(DMA_MEMCPY, mv78xx0_xor00_data.cap_mask);
+ dma_cap_set(DMA_XOR, mv78xx0_xor00_data.cap_mask);
+ platform_device_register(&mv78xx0_xor00_channel);
+
+ dma_cap_set(DMA_MEMCPY, mv78xx0_xor01_data.cap_mask);
+ dma_cap_set(DMA_MEMSET, mv78xx0_xor01_data.cap_mask);
+ dma_cap_set(DMA_XOR, mv78xx0_xor01_data.cap_mask);
+ platform_device_register(&mv78xx0_xor01_channel);
+}
+
+
+/*****************************************************************************
+ * Watchdog
+ ****************************************************************************/
+static struct orion_wdt_platform_data mv78xx0_wdt_data = {
+ .tclk = 0,
+};
+
+static struct platform_device mv78xx0_wdt_device = {
+ .name = "orion_wdt",
+ .id = -1,
+ .dev = {
+ .platform_data = &mv78xx0_wdt_data,
+ },
+ .num_resources = 0,
+};
+
+void __init mv78xx0_wdt_init(void)
+{
+ mv78xx0_wdt_data.tclk = get_tclk();
+ platform_device_register(&mv78xx0_wdt_device);
+}
+
/*****************************************************************************
* Time handling
mv78xx0_uart1_data[0].uartclk = tclk;
mv78xx0_uart2_data[0].uartclk = tclk;
mv78xx0_uart3_data[0].uartclk = tclk;
+ mv78x00_spi_plat_data.tclk = tclk;
}