#define MV78XX0_REGS_VIRT_BASE 0xfef00000
#define MV78XX0_REGS_SIZE SZ_1M
+#define MV78XX0_SRAM_PHYS_BASE 0xf4000000
+#define MV78XX0_SRAM_SIZE SZ_2K
+
#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
#define MV78XX0_PCIE_MEM_SIZE 0x30000000
+#define MV78XX0_NAND_MEM_PHYS_BASE 0xfa000000
+#define MV78XX0_NAND_MEM_SIZE SZ_1K
+
+#define MV78XX0_BOOTCS_MEM_PHY_BASE 0xfc000000
+#define MV78XX0_BOOTCS_MEM_SIZE SZ_64M
+
/*
* Core-specific peripheral registers.
*/
#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030)
#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034)
+#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)
#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100)
#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000)
#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000)
+#define XOR0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x60900)
+#define XOR0_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x60900)
+#define XOR0_HIGH_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x60B00)
+#define XOR0_HIGH_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x60B00)
+
#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000)
#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000)
#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000)
#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000)
+#define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x90000)
+
#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000)
/*