arm: mvebu: Disable L2 cache before enabling d-cache

[karo-tx-uboot.git] / arch / arm / mach-mvebu / cpu.c

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index eca5e2176cdefe351f0be99b577fc8aba796fb1f..417fc35149b538b83911140f79a711d22f095c67 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <netdev.h>
 #include <asm/io.h>
+#include <asm/pl310.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 
@@ -216,10 +217,22 @@ int arch_misc_init(void)
 #ifdef CONFIG_MVNETA
 int cpu_eth_init(bd_t *bis)
 {
-       mvneta_initialize(bis, MVEBU_EGIGA0_BASE, 0, CONFIG_PHY_BASE_ADDR + 0);
-       mvneta_initialize(bis, MVEBU_EGIGA1_BASE, 1, CONFIG_PHY_BASE_ADDR + 1);
-       mvneta_initialize(bis, MVEBU_EGIGA2_BASE, 2, CONFIG_PHY_BASE_ADDR + 2);
-       mvneta_initialize(bis, MVEBU_EGIGA3_BASE, 3, CONFIG_PHY_BASE_ADDR + 3);
+       u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
+                           MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
+       u8 phy_addr[] = CONFIG_PHY_ADDR;
+       int i;
+
+       /*
+        * Only Armada XP supports all 4 ethernet interfaces. A38x has
+        * slightly different base addresses for its 2-3 interfaces.
+        */
+       if (mvebu_soc_family() != MVEBU_SOC_AXP) {
+               enet_base[1] = MVEBU_EGIGA2_BASE;
+               enet_base[2] = MVEBU_EGIGA3_BASE;
+       }
+
+       for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
+               mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
 
        return 0;
 }
@@ -228,6 +241,16 @@ int cpu_eth_init(bd_t *bis)
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
 {
+       struct pl310_regs *const pl310 =
+               (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+       /* First disable L2 cache - may still be enable from BootROM */
+       if (mvebu_soc_family() == MVEBU_SOC_A38X)
+               clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+       /* Avoid problem with e.g. neta ethernet driver */
+       invalidate_dcache_all();
+
        /* Enable D-cache. I-cache is already enabled in start.S */
        dcache_enable();
 }