arm64: mvebu: Add support for the Marvell Armada 3700 SoC

[karo-tx-uboot.git] / arch / arm / mach-mvebu / include / mach / soc.h

diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index a8a6b27d802b7c4e4dc9caa512e49b9daaf72c87..063d6ccabd88e983e81483de499b6c75b27f699c 100644 (file)
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -11,13 +11,17 @@
 #ifndef _MVEBU_SOC_H
 #define _MVEBU_SOC_H
 
-#define BIT(x)                 (1 << (x))
-
+#define SOC_MV78230_ID         0x7823
+#define SOC_MV78260_ID         0x7826
 #define SOC_MV78460_ID         0x7846
+#define SOC_88F6720_ID         0x6720
 #define SOC_88F6810_ID         0x6810
 #define SOC_88F6820_ID         0x6820
 #define SOC_88F6828_ID         0x6828
 
+/* A375 revisions */
+#define MV_88F67XX_A0_ID       0x3
+
 /* A38x revisions */
 #define MV_88F68XX_Z1_ID       0x0
 #define MV_88F68XX_A0_ID       0x4
@@ -33,12 +37,13 @@
 /* SOC specific definations */
 #define INTREG_BASE            0xd0000000
 #define INTREG_BASE_ADDR_REG   (INTREG_BASE + 0x20080)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_MVEBU_DDR_A38X)
+#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700)
 /*
- * On A38x switching the regs base address without running from
- * SDRAM doesn't seem to work. So let the SPL still use the
- * default base address and switch to the new address in the
- * main u-boot later.
+ * The SPL U-Boot version still runs with the default
+ * address for the internal registers, configured by
+ * the BootROM. Only the main U-Boot version uses the
+ * new internal register base address, that also is
+ * required for the Linux kernel.
  */
 #define SOC_REGS_PHY_BASE      0xd0000000
 #else
@@ -49,10 +54,8 @@
 #define MVEBU_SDRAM_SCRATCH    (MVEBU_REGISTER(0x01504))
 #define MVEBU_L2_CACHE_BASE    (MVEBU_REGISTER(0x08000))
 #define CONFIG_SYS_PL310_BASE  MVEBU_L2_CACHE_BASE
-#define MVEBU_SPI_BASE         (MVEBU_REGISTER(0x10600))
 #define MVEBU_TWSI_BASE                (MVEBU_REGISTER(0x11000))
-#define MVEBU_UART0_BASE       (MVEBU_REGISTER(0x12000))
-#define MVEBU_UART1_BASE       (MVEBU_REGISTER(0x12100))
+#define MVEBU_TWSI1_BASE       (MVEBU_REGISTER(0x11100))
 #define MVEBU_MPP_BASE         (MVEBU_REGISTER(0x18000))
 #define MVEBU_GPIO0_BASE       (MVEBU_REGISTER(0x18100))
 #define MVEBU_GPIO1_BASE       (MVEBU_REGISTER(0x18140))
@@ -62,17 +65,15 @@
 #define MVEBU_CPU_WIN_BASE     (MVEBU_REGISTER(0x20000))
 #define MVEBU_SDRAM_BASE       (MVEBU_REGISTER(0x20180))
 #define MVEBU_TIMER_BASE       (MVEBU_REGISTER(0x20300))
-#define MVEBU_EGIGA2_BASE      (MVEBU_REGISTER(0x30000))
-#define MVEBU_EGIGA3_BASE      (MVEBU_REGISTER(0x34000))
 #define MVEBU_REG_PCIE_BASE    (MVEBU_REGISTER(0x40000))
 #define MVEBU_AXP_USB_BASE      (MVEBU_REGISTER(0x50000))
 #define MVEBU_USB20_BASE       (MVEBU_REGISTER(0x58000))
-#define MVEBU_EGIGA0_BASE      (MVEBU_REGISTER(0x70000))
-#define MVEBU_EGIGA1_BASE      (MVEBU_REGISTER(0x74000))
 #define MVEBU_AXP_SATA_BASE    (MVEBU_REGISTER(0xa0000))
 #define MVEBU_SATA0_BASE       (MVEBU_REGISTER(0xa8000))
 #define MVEBU_NAND_BASE                (MVEBU_REGISTER(0xd0000))
 #define MVEBU_SDIO_BASE                (MVEBU_REGISTER(0xd8000))
+#define MVEBU_LCD_BASE         (MVEBU_REGISTER(0xe0000))
+#define MVEBU_DFX_BASE         (MVEBU_REGISTER(0xe4000))
 
 #define SOC_COHERENCY_FABRIC_CTRL_REG  (MVEBU_REGISTER(0x20200))
 #define MBUS_ERR_PROP_EN       (1 << 8)
@@ -92,6 +93,7 @@
 #define SPI_PUP_EN             BIT(5)
 
 #define MVEBU_CORE_DIV_CLK_CTRL(i)     (MVEBU_CLOCK_BASE + ((i) * 0x8))
+#define MVEBU_DFX_DIV_CLK_CTRL(i)      (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
 #define NAND_ECC_DIVCKL_RATIO_OFFS     8
 #define NAND_ECC_DIVCKL_RATIO_MASK     (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
 
@@ -103,4 +105,62 @@
 #define MVCPU_WIN_ENABLE       CPU_WIN_ENABLE
 #define MVCPU_WIN_DISABLE      CPU_WIN_DISABLE
 
+#define COMPHY_REFCLK_ALIGNMENT        (MVEBU_REGISTER(0x182f8))
+
+/* BootROM error register (also includes some status infos) */
+#define CONFIG_BOOTROM_ERR_REG (MVEBU_REGISTER(0x182d0))
+#define BOOTROM_ERR_MODE_OFFS  28
+#define BOOTROM_ERR_MODE_MASK  (0xf << BOOTROM_ERR_MODE_OFFS)
+#define BOOTROM_ERR_MODE_UART  0x6
+
+#if defined(CONFIG_ARMADA_375)
+/* SAR values for Armada 375 */
+#define CONFIG_SAR_REG         (MVEBU_REGISTER(0xe8200))
+#define CONFIG_SAR2_REG                (MVEBU_REGISTER(0xe8204))
+
+#define SAR_CPU_FREQ_OFFS      17
+#define SAR_CPU_FREQ_MASK      (0x1f << SAR_CPU_FREQ_OFFS)
+
+#define BOOT_DEV_SEL_OFFS      3
+#define BOOT_DEV_SEL_MASK      (0x3f << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART         0x30
+#define BOOT_FROM_SPI          0x38
+#elif defined(CONFIG_ARMADA_38X)
+/* SAR values for Armada 38x */
+#define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18600))
+
+#define SAR_CPU_FREQ_OFFS      10
+#define SAR_CPU_FREQ_MASK      (0x1f << SAR_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS   4
+#define SAR_BOOT_DEVICE_MASK   (0x1f << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS      4
+#define BOOT_DEV_SEL_MASK      (0x3f << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART         0x28
+#define BOOT_FROM_SPI          0x32
+#define BOOT_FROM_MMC          0x30
+#define BOOT_FROM_MMC_ALT      0x31
+#else
+/* SAR values for Armada XP */
+#define CONFIG_SAR_REG         (MVEBU_REGISTER(0x18230))
+#define CONFIG_SAR2_REG                (MVEBU_REGISTER(0x18234))
+
+#define SAR_CPU_FREQ_OFFS      21
+#define SAR_CPU_FREQ_MASK      (0x7 << SAR_CPU_FREQ_OFFS)
+#define SAR_FFC_FREQ_OFFS      24
+#define SAR_FFC_FREQ_MASK      (0xf << SAR_FFC_FREQ_OFFS)
+#define SAR2_CPU_FREQ_OFFS     20
+#define SAR2_CPU_FREQ_MASK     (0x1 << SAR2_CPU_FREQ_OFFS)
+#define SAR_BOOT_DEVICE_OFFS   5
+#define SAR_BOOT_DEVICE_MASK   (0xf << SAR_BOOT_DEVICE_OFFS)
+
+#define BOOT_DEV_SEL_OFFS      5
+#define BOOT_DEV_SEL_MASK      (0xf << BOOT_DEV_SEL_OFFS)
+
+#define BOOT_FROM_UART         0x2
+#define BOOT_FROM_SPI          0x3
+#endif
+
 #endif /* _MVEBU_SOC_H */