ARM: OMAP4: PM: Add init api for DPLL nodes

[linux-beck.git] / arch / arm / mach-omap2 / clock.h

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 4df7aa43ef44107d26ce5c1b9bdf54b449916e18..93c48df3b5b1f864587e23474731ed9f4399c5fb 100644 (file)
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -36,6 +36,12 @@
 #define OMAP3XXX_EN_DPLL_FRBYPASS              0x6
 #define OMAP3XXX_EN_DPLL_LOCKED                        0x7
 
+/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
+#define OMAP4XXX_EN_DPLL_MNBYPASS              0x4
+#define OMAP4XXX_EN_DPLL_LPBYPASS              0x5
+#define OMAP4XXX_EN_DPLL_FRBYPASS              0x6
+#define OMAP4XXX_EN_DPLL_LOCKED                        0x7
+
 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
 #define DPLL_LOW_POWER_STOP    0x1
 #define DPLL_LOW_POWER_BYPASS  0x5
@@ -76,6 +82,7 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 u32 omap2_get_dpll_rate(struct clk *clk);
+void omap2_init_dpll_parent(struct clk *clk);
 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
 void omap2_clk_prepare_for_reboot(void);
 int omap2_dflt_clk_enable(struct clk *clk);