ARM: OMAP2: clock: Cleanup !CONFIG_COMMON_CLK parts

[karo-tx-linux.git] / arch / arm / mach-omap2 / clock2420_data.c

diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index c3cde1a2b6de6d71956043cbd72054b6f3052438..ec6d5396575388ff588d906f863dde136da3b968 100644 (file)
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1,7 +1,7 @@
 /*
  * OMAP2420 clock data
  *
- * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
  * Copyright (C) 2004-2011 Nokia Corporation
  *
  * Contacts:
@@ -18,14 +18,12 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 
-#include <plat/clkdev_omap.h>
-
 #include "soc.h"
 #include "iomap.h"
 #include "clock.h"
 #include "clock2xxx.h"
 #include "opp2xxx.h"
-#include "cm2xxx_3xxx.h"
+#include "cm2xxx.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 #include "cm-regbits-24xx.h"
@@ -56,14 +54,12 @@ static struct clk func_32k_ck = {
        .name           = "func_32k_ck",
        .ops            = &clkops_null,
        .rate           = 32768,
-       .clkdm_name     = "wkup_clkdm",
 };
 
 static struct clk secure_32k_ck = {
        .name           = "secure_32k_ck",
        .ops            = &clkops_null,
        .rate           = 32768,
-       .clkdm_name     = "wkup_clkdm",
 };
 
 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
@@ -87,7 +83,6 @@ static struct clk alt_ck = {          /* Typical 54M or 48M, may not exist */
        .name           = "alt_ck",
        .ops            = &clkops_null,
        .rate           = 54000000,
-       .clkdm_name     = "wkup_clkdm",
 };
 
 /* Optional external clock input for McBSP CLKS */
@@ -126,6 +121,7 @@ static struct clk dpll_ck = {
        .name           = "dpll_ck",
        .ops            = &clkops_omap2xxx_dpll_ops,
        .parent         = &sys_ck,              /* Can be func_32k also */
+       .init           = &omap2xxx_clkt_dpllcore_init,
        .dpll_data      = &dpll_dd,
        .clkdm_name     = "wkup_clkdm",
        .recalc         = &omap2_dpllcore_recalc,
@@ -180,7 +176,6 @@ static struct clk func_54m_ck = {
        .name           = "func_54m_ck",
        .ops            = &clkops_null,
        .parent         = &apll54_ck,   /* can also be alt_clk */
-       .clkdm_name     = "wkup_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
        .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
@@ -241,7 +236,6 @@ static struct clk func_12m_ck = {
        .ops            = &clkops_null,
        .parent         = &func_48m_ck,
        .fixed_div      = 4,
-       .clkdm_name     = "wkup_clkdm",
        .recalc         = &omap_fixed_divisor_recalc,
 };
 
@@ -323,7 +317,6 @@ static struct clk sys_clkout = {
        .name           = "sys_clkout",
        .ops            = &clkops_null,
        .parent         = &sys_clkout_src,
-       .clkdm_name     = "wkup_clkdm",
        .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
        .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
        .clksel         = sys_clkout_clksel,
@@ -359,7 +352,6 @@ static struct clk sys_clkout2 = {
        .name           = "sys_clkout2",
        .ops            = &clkops_null,
        .parent         = &sys_clkout2_src,
-       .clkdm_name     = "wkup_clkdm",
        .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
        .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
        .clksel         = sys_clkout2_clksel,
@@ -407,7 +399,6 @@ static struct clk mpu_ck = {        /* Control cpu */
        .name           = "mpu_ck",
        .ops            = &clkops_null,
        .parent         = &core_ck,
-       .clkdm_name     = "mpu_clkdm",
        .init           = &omap2_init_clksel_parent,
        .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
        .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
@@ -541,7 +532,6 @@ static struct clk core_l3_ck = {    /* Used for ick and fck, interconnect */
        .name           = "core_l3_ck",
        .ops            = &clkops_null,
        .parent         = &core_ck,
-       .clkdm_name     = "core_l3_clkdm",
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
        .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
        .clksel         = core_l3_clksel,
@@ -597,7 +587,6 @@ static struct clk l4_ck = {         /* used both as an ick and fck */
        .name           = "l4_ck",
        .ops            = &clkops_null,
        .parent         = &core_l3_ck,
-       .clkdm_name     = "core_l4_clkdm",
        .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
        .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
        .clksel         = l4_clksel,
@@ -1926,17 +1915,12 @@ static struct omap_clk omap2420_clks[] = {
 
 int __init omap2420_clk_init(void)
 {
-       const struct prcm_config *prcm;
        struct omap_clk *c;
-       u32 clkrate;
 
        prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
-       cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
        cpu_mask = RATE_IN_242X;
        rate_table = omap2420_rate_table;
 
-       clk_init(&omap2_clk_functions);
-
        for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
             c++)
                clk_preinit(c->lk.clk);
@@ -1953,20 +1937,13 @@ int __init omap2420_clk_init(void)
                omap2_init_clk_clkdm(c->lk.clk);
        }
 
+       omap2xxx_clkt_vps_late_init();
+
        /* Disable autoidle on all clocks; let the PM code enable it later */
        omap_clk_disable_autoidle_all();
 
-       /* Check the MPU rate set by bootloader */
-       clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
-       for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-               if (!(prcm->flags & cpu_mask))
-                       continue;
-               if (prcm->xtal_speed != sys_ck.rate)
-                       continue;
-               if (prcm->dpll_speed <= clkrate)
-                       break;
-       }
-       curr_prcm_set = prcm;
+       /* XXX Can this be done from the virt_prcm_set clk init function? */
+       omap2xxx_clkt_vps_check_bootloader_rates();
 
        recalculate_root_clocks();
 
@@ -1980,11 +1957,6 @@ int __init omap2420_clk_init(void)
         */
        clk_enable_init_clocks();
 
-       /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
-       vclk = clk_get(NULL, "virt_prcm_set");
-       sclk = clk_get(NULL, "sys_ck");
-       dclk = clk_get(NULL, "dpll_ck");
-
        return 0;
 }