[ARM] omap: clks: call recalc after any rate change

[mv-sheeva.git] / arch / arm / mach-omap2 / clock24xx.c

diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index 421728a7f9032ed829a1c9372baa368461a53fdb..4564ae32ae020fc5f8ee265f648ed52acc4ae5df 100644 (file)
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -33,7 +33,7 @@
 #include <asm/div64.h>
 #include <asm/clkdev.h>
 
-#include "memory.h"
+#include <mach/sdrc.h>
 #include "clock.h"
 #include "prm.h"
 #include "prm-regbits-24xx.h"
@@ -389,9 +389,9 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
        mult &= OMAP24XX_CORE_CLK_SRC_MASK;
 
        if ((rate == (cur_rate / 2)) && (mult == 2)) {
-               omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+               omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
        } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
-               omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+               omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
        } else if (rate != cur_rate) {
                valid_rate = omap2_dpllcore_round_rate(rate);
                if (valid_rate != rate)
@@ -430,17 +430,17 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
                if (rate == curr_prcm_set->xtal_speed)  /* If asking for 1-1 */
                        bypass = 1;
 
-               omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */
+               /* For omap2xxx_sdrc_init_params() */
+               omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 
                /* Force dll lock mode */
                omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr,
                               bypass);
 
                /* Errata: ret dll entry state */
-               omap2_init_memory_params(omap2_dll_force_needed());
-               omap2_reprogram_sdrc(done_rate, 0);
+               omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+               omap2xxx_sdrc_reprogram(done_rate, 0);
        }
-       omap2_dpllcore_recalc(&dpll_ck);
        ret = 0;
 
 dpll_exit:
@@ -525,9 +525,9 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
        cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);
 
        if (prcm->dpll_speed == cur_rate / 2) {
-               omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1);
+               omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1);
        } else if (prcm->dpll_speed == cur_rate * 2) {
-               omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+               omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
        } else if (prcm->dpll_speed != cur_rate) {
                local_irq_save(flags);
 
@@ -558,22 +558,60 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
                        cm_write_mod_reg(prcm->cm_clksel_mdm,
                                         OMAP2430_MDM_MOD, CM_CLKSEL);
 
-               /* x2 to enter init_mem */
-               omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
+               /* x2 to enter omap2xxx_sdrc_init_params() */
+               omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1);
 
                omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr,
                               bypass);
 
-               omap2_init_memory_params(omap2_dll_force_needed());
-               omap2_reprogram_sdrc(done_rate, 0);
+               omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());
+               omap2xxx_sdrc_reprogram(done_rate, 0);
 
                local_irq_restore(flags);
        }
-       omap2_dpllcore_recalc(&dpll_ck);
 
        return 0;
 }
 
+#ifdef CONFIG_CPU_FREQ
+/*
+ * Walk PRCM rate table and fillout cpufreq freq_table
+ */
+static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)];
+
+void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
+{
+       struct prcm_config *prcm;
+       int i = 0;
+
+       for (prcm = rate_table; prcm->mpu_speed; prcm++) {
+               if (!(prcm->flags & cpu_mask))
+                       continue;
+               if (prcm->xtal_speed != sys_ck.rate)
+                       continue;
+
+               /* don't put bypass rates in table */
+               if (prcm->dpll_speed == prcm->xtal_speed)
+                       continue;
+
+               freq_table[i].index = i;
+               freq_table[i].frequency = prcm->mpu_speed / 1000;
+               i++;
+       }
+
+       if (i == 0) {
+               printk(KERN_WARNING "%s: failed to initialize frequency "
+                      "table\n", __func__);
+               return;
+       }
+
+       freq_table[i].index = i;
+       freq_table[i].frequency = CPUFREQ_TABLE_END;
+
+       *table = &freq_table[0];
+}
+#endif
+
 static struct clk_functions omap2_clk_functions = {
        .clk_enable             = omap2_clk_enable,
        .clk_disable            = omap2_clk_disable,
@@ -581,6 +619,9 @@ static struct clk_functions omap2_clk_functions = {
        .clk_set_rate           = omap2_clk_set_rate,
        .clk_set_parent         = omap2_clk_set_parent,
        .clk_disable_unused     = omap2_clk_disable_unused,
+#ifdef CONFIG_CPU_FREQ
+       .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table,
+#endif
 };
 
 static u32 omap2_get_apll_clkin(void)
@@ -645,7 +686,7 @@ static int __init omap2_clk_arch_init(void)
        if (!mpurate)
                return -EINVAL;
 
-       if (omap2_select_table_rate(&virt_prcm_set, mpurate))
+       if (clk_set_rate(&virt_prcm_set, mpurate))
                printk(KERN_ERR "Could not find matching MPU rate\n");
 
        recalculate_root_clocks();