.name = "dpll_abe_ck",
.parent = &abe_dpll_refclk_mux_ck,
.dpll_data = &dpll_abe_dd,
+ .init = &omap2_init_dpll_parent,
.ops = &clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.name = "dpll_core_ck",
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_core_dd,
+ .init = &omap2_init_dpll_parent,
.ops = &clkops_null,
.recalc = &omap3_dpll_recalc,
.flags = CLOCK_IN_OMAP4430,
.name = "dpll_iva_ck",
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_iva_dd,
+ .init = &omap2_init_dpll_parent,
.ops = &clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.name = "dpll_mpu_ck",
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_mpu_dd,
+ .init = &omap2_init_dpll_parent,
.ops = &clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.name = "dpll_per_ck",
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_per_dd,
+ .init = &omap2_init_dpll_parent,
.ops = &clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.name = "dpll_unipro_ck",
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_unipro_dd,
+ .init = &omap2_init_dpll_parent,
.ops = &clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,
.name = "dpll_usb_ck",
.parent = &dpll_sys_ref_clk,
.dpll_data = &dpll_usb_dd,
+ .init = &omap2_init_dpll_parent,
.ops = &clkops_noncore_dpll_ops,
.recalc = &omap3_dpll_recalc,
.round_rate = &omap2_dpll_round_rate,