/* CM_CLKSEL1_PLL_IVA2 */
#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)
+#define OMAP3430_IVA2_CLK_SRC_WIDTH 3
#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
/* CM_CLKSEL2_PLL_IVA2 */
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
+#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5
/* CM_CLKSTCTRL_IVA2 */
#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
/* CM_IDLEST_PLL_MPU */
#define OMAP3430_ST_MPU_CLK_SHIFT 0
#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
+#define OMAP3430_ST_MPU_CLK_WIDTH 1
/* CM_AUTOIDLE_PLL_MPU */
#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
/* CM_CLKSEL1_PLL_MPU */
#define OMAP3430_MPU_CLK_SRC_SHIFT 19
#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)
+#define OMAP3430_MPU_CLK_SRC_WIDTH 3
#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
/* CM_CLKSEL2_PLL_MPU */
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
+#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5
/* CM_CLKSTCTRL_MPU */
#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
#define OMAP3430_CLKSEL_L4_SHIFT 2
#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
+#define OMAP3430_CLKSEL_L4_WIDTH 2
#define OMAP3430_CLKSEL_L3_SHIFT 0
#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
+#define OMAP3430_CLKSEL_L3_WIDTH 2
#define OMAP3630_CLKSEL_96M_SHIFT 12
#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
+#define OMAP3630_CLKSEL_96M_WIDTH 2
/* CM_CLKSTCTRL_CORE */
#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
#define OMAP3430_CLKSEL_RM_SHIFT 1
#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
+#define OMAP3430_CLKSEL_RM_WIDTH 2
#define OMAP3430_CLKSEL_GPT1_SHIFT 0
#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
+#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5
#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
#define OMAP3430_SOURCE_96M_SHIFT 6
#define OMAP3430_SOURCE_96M_MASK (1 << 6)
+#define OMAP3430_SOURCE_96M_WIDTH 1
#define OMAP3430_SOURCE_54M_SHIFT 5
#define OMAP3430_SOURCE_54M_MASK (1 << 5)
+#define OMAP3430_SOURCE_54M_WIDTH 1
#define OMAP3430_SOURCE_48M_SHIFT 3
#define OMAP3430_SOURCE_48M_MASK (1 << 3)
/* CM_CLKSEL3_PLL */
#define OMAP3430_DIV_96M_SHIFT 0
#define OMAP3430_DIV_96M_MASK (0x1f << 0)
+#define OMAP3430_DIV_96M_WIDTH 5
#define OMAP3630_DIV_96M_MASK (0x3f << 0)
+#define OMAP3630_DIV_96M_WIDTH 6
/* CM_CLKSEL4_PLL */
#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
/* CM_CLKSEL5_PLL */
#define OMAP3430ES2_DIV_120M_SHIFT 0
#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
+#define OMAP3430ES2_DIV_120M_WIDTH 5
/* CM_CLKOUT_CTRL */
#define OMAP3430_CLKOUT2_EN_SHIFT 7
#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)
#define OMAP3430_CLKOUT2_DIV_SHIFT 3
#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
+#define OMAP3430_CLKOUT2_DIV_WIDTH 3
#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
/* CM_CLKSEL_DSS */
#define OMAP3430_CLKSEL_TV_SHIFT 8
#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
+#define OMAP3430_CLKSEL_TV_WIDTH 5
#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)
+#define OMAP3630_CLKSEL_TV_WIDTH 6
#define OMAP3430_CLKSEL_DSS1_SHIFT 0
#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
+#define OMAP3430_CLKSEL_DSS1_WIDTH 5
#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)
+#define OMAP3630_CLKSEL_DSS1_WIDTH 6
/* CM_SLEEPDEP_DSS specific bits */
/* CM_CLKSEL_CAM */
#define OMAP3430_CLKSEL_CAM_SHIFT 0
#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
+#define OMAP3430_CLKSEL_CAM_WIDTH 5
#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)
+#define OMAP3630_CLKSEL_CAM_WIDTH 6
/* CM_SLEEPDEP_CAM specific bits */
/* CM_CLKSEL1_EMU */
#define OMAP3430_DIV_DPLL4_SHIFT 24
#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
+#define OMAP3430_DIV_DPLL4_WIDTH 5
#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)
+#define OMAP3630_DIV_DPLL4_WIDTH 6
#define OMAP3430_DIV_DPLL3_SHIFT 16
#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
+#define OMAP3430_DIV_DPLL3_WIDTH 5
#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
+#define OMAP3430_CLKSEL_TRACECLK_WIDTH 3
#define OMAP3430_CLKSEL_PCLK_SHIFT 8
#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
+#define OMAP3430_CLKSEL_PCLK_WIDTH 3
#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
+#define OMAP3430_CLKSEL_PCLKX2_WIDTH 2
#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
+#define OMAP3430_CLKSEL_ATCLK_WIDTH 2
#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
+#define OMAP3430_TRACE_MUX_CTRL_WIDTH 2
#define OMAP3430_MUX_CTRL_SHIFT 0
#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
+#define OMAP3430_MUX_CTRL_WIDTH 2
/* CM_CLKSTCTRL_EMU */
#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
projects / karo-tx-linux.git / blobdiff