Merge branch 'omap4_and_sdrc_2.6.27' of git://git.pwsan.com/linux-2.6 into omap-for...

[karo-tx-linux.git] / arch / arm / mach-omap2 / id.c

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index e8256a2ed8e782dd56a7bfa674b98886a9f63e71..0412233da2b377c29f89faa158c161ade08cf925 100644 (file)
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -60,7 +60,7 @@ int omap_type(void)
        } else if (cpu_is_omap34xx()) {
                val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
        } else if (cpu_is_omap44xx()) {
-               val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS);
+               val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
        } else {
                pr_err("Cannot detect omap type!\n");
                goto out;
@@ -284,8 +284,8 @@ static void __init omap3_check_revision(void)
                default:
                        omap_revision =  OMAP3630_REV_ES1_2;
                        omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
-                       break;
                }
+               break;
        default:
                /* Unknown default to latest silicon rev as default*/
                omap_revision =  OMAP3630_REV_ES1_2;
@@ -298,7 +298,6 @@ static void __init omap4_check_revision(void)
        u32 idcode;
        u16 hawkeye;
        u8 rev;
-       char *rev_name = "ES1.0";
 
        /*
         * The IC rev detection is done with hawkeye and rev.
@@ -309,14 +308,39 @@ static void __init omap4_check_revision(void)
        hawkeye = (idcode >> 12) & 0xffff;
        rev = (idcode >> 28) & 0xff;
 
-       if ((hawkeye == 0xb852) && (rev == 0x0)) {
-               omap_revision = OMAP4430_REV_ES1_0;
-               omap_chip.oc |= CHIP_IS_OMAP4430ES1;
-               pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
-               return;
+       /*
+        * Few initial ES2.0 samples IDCODE is same as ES1.0
+        * Use ARM register to detect the correct ES version
+        */
+       if (!rev) {
+               idcode = read_cpuid(CPUID_ID);
+               rev = (idcode & 0xf) - 1;
+       }
+
+       switch (hawkeye) {
+       case 0xb852:
+               switch (rev) {
+               case 0:
+                       omap_revision = OMAP4430_REV_ES1_0;
+                       omap_chip.oc |= CHIP_IS_OMAP4430ES1;
+                       break;
+               case 1:
+                       omap_revision = OMAP4430_REV_ES2_0;
+                       omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+                       break;
+               default:
+                       omap_revision = OMAP4430_REV_ES2_0;
+                       omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+       }
+       break;
+       default:
+               /* Unknown default to latest silicon rev as default*/
+               omap_revision = OMAP4430_REV_ES2_0;
+               omap_chip.oc |= CHIP_IS_OMAP4430ES2;
        }
 
-       pr_err("Unknown OMAP4 CPU id\n");
+       pr_info("OMAP%04x ES%d.0\n",
+                       omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
 }
 
 #define OMAP3_SHOW_FEATURE(feat)               \