Merge tag 'renesas-sh-drivers-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel...

[karo-tx-linux.git] / arch / arm / mach-prima2 / rstc.c

diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 4887a2a4c698a7f5b82e0b511af84615cee7dd86..3dffcb2d714ee8034046c1e2f501e21d43e6b68b 100644 (file)
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -36,27 +36,33 @@ static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
 
        if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
                /*
-                * Writing 1 to this bit resets corresponding block. Writing 0 to this
-                * bit de-asserts reset signal of the corresponding block.
-                * datasheet doesn't require explicit delay between the set and clear
-                * of reset bit. it could be shorter if tests pass.
+                * Writing 1 to this bit resets corresponding block.
+                * Writing 0 to this bit de-asserts reset signal of the
+                * corresponding block. datasheet doesn't require explicit
+                * delay between the set and clear of reset bit. it could
+                * be shorter if tests pass.
                 */
-               writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | (1 << reset_bit),
+               writel(readl(sirfsoc_rstc_base +
+                       (reset_bit / 32) * 4) | (1 << reset_bit),
                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
-               msleep(10);
-               writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~(1 << reset_bit),
+               msleep(20);
+               writel(readl(sirfsoc_rstc_base +
+                       (reset_bit / 32) * 4) & ~(1 << reset_bit),
                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
        } else {
                /*
                 * For MARCO and POLO
-                * Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
-                * register de-asserts reset signal of the corresponding block.
-                * datasheet doesn't require explicit delay between the set and clear
-                * of reset bit. it could be shorter if tests pass.
+                * Writing 1 to SET register resets corresponding block.
+                * Writing 1 to CLEAR register de-asserts reset signal of the
+                * corresponding block.
+                * datasheet doesn't require explicit delay between the set and
+                * clear of reset bit. it could be shorter if tests pass.
                 */
-               writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
-               msleep(10);
-               writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
+               writel(1 << reset_bit,
+                       sirfsoc_rstc_base + (reset_bit / 32) * 8);
+               msleep(20);
+               writel(1 << reset_bit,
+                       sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
        }
 
        mutex_unlock(&rstc_lock);