Merge branch 'samsung/cleanup' into samsung/driver

[linux-beck.git] / arch / arm / mach-s5p64x0 / clock-s5p6450.c

diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index bd9d1e6fc5e29c5316e56900d6c2c07bf4f76a56..5bf607ccbaf71fde85608c106a89a8db05483d3d 100644 (file)
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -413,36 +413,6 @@ static struct clksrc_clk clk_sclk_audio0 = {
 
 static struct clksrc_clk clksrcs[] = {
        {
-               .clk    = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.0",
-                       .ctrlbit        = (1 << 24),
-                       .enable         = s5p64x0_sclk_ctrl,
-               },
-               .sources = &clkset_group2,
-               .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
-               .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
-       }, {
-               .clk    = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.1",
-                       .ctrlbit        = (1 << 25),
-                       .enable         = s5p64x0_sclk_ctrl,
-               },
-               .sources = &clkset_group2,
-               .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
-               .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
-       }, {
-               .clk    = {
-                       .name           = "sclk_mmc",
-                       .devname        = "s3c-sdhci.2",
-                       .ctrlbit        = (1 << 26),
-                       .enable         = s5p64x0_sclk_ctrl,
-               },
-               .sources = &clkset_group2,
-               .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
-               .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
-       }, {
                .clk    = {
                        .name           = "sclk_fimc",
                        .ctrlbit        = (1 << 10),
@@ -508,6 +478,42 @@ static struct clksrc_clk clksrcs[] = {
        },
 };
 
+static struct clksrc_clk clk_sclk_mmc0 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.0",
+               .ctrlbit        = (1 << 24),
+               .enable         = s5p64x0_sclk_ctrl,
+       },
+       .sources = &clkset_group2,
+       .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+       .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc1 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.1",
+               .ctrlbit        = (1 << 25),
+               .enable         = s5p64x0_sclk_ctrl,
+       },
+       .sources = &clkset_group2,
+       .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+       .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_mmc2 = {
+       .clk    = {
+               .name           = "sclk_mmc",
+               .devname        = "s3c-sdhci.2",
+               .ctrlbit        = (1 << 26),
+               .enable         = s5p64x0_sclk_ctrl,
+       },
+       .sources = &clkset_group2,
+       .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+       .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+};
+
 static struct clksrc_clk clk_sclk_uclk = {
        .clk    = {
                .name           = "uclk1",
@@ -547,6 +553,9 @@ static struct clksrc_clk *clksrc_cdev[] = {
        &clk_sclk_uclk,
        &clk_sclk_spi0,
        &clk_sclk_spi1,
+       &clk_sclk_mmc0,
+       &clk_sclk_mmc1,
+       &clk_sclk_mmc2,
 };
 
 static struct clk_lookup s5p6450_clk_lookup[] = {
@@ -555,6 +564,9 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+       CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+       CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+       CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
 };
 
 /* Clock initialization code */