Merge branch 'master' of git://git.denx.de/u-boot-i2c

[karo-tx-uboot.git] / arch / arm / mach-socfpga / misc.c

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 9b43b92f5bcd5faba60f691dc1cced2321b69593..5cbd8a432558207e776d7f02dd5958ea20753465 100644 (file)
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -16,7 +16,6 @@
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/scan_manager.h>
 #include <asm/arch/system_manager.h>
-#include <asm/arch/dwmmc.h>
 #include <asm/arch/nic301.h>
 #include <asm/arch/scu.h>
 #include <asm/pl310.h>
@@ -77,7 +76,8 @@ void v7_outer_cache_disable(void)
  * DesignWare Ethernet initialization
  */
 #ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id)
+static void dwmac_deassert_reset(const unsigned int of_reset_id,
+                                const u32 phymode)
 {
        u32 physhift, reset;
 
@@ -98,16 +98,41 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id)
 
        /* configure to PHY interface select choosed */
        setbits_le32(&sysmgr_regs->emacgrp_ctrl,
-                    SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+                    phymode << physhift);
 
        /* Release the EMAC controller from reset */
        socfpga_per_reset(reset, 0);
 }
 
-int cpu_eth_init(bd_t *bis)
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+       if (!phymode)
+               return -EINVAL;
+
+       if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+               *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+               return 0;
+       }
+
+       if (!strcmp(phymode, "rgmii")) {
+               *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+               return 0;
+       }
+
+       if (!strcmp(phymode, "rmii")) {
+               *modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+               return 0;
+       }
+
+       return -EINVAL;
+}
+
+static int socfpga_eth_reset(void)
 {
        const void *fdt = gd->fdt_blob;
        struct fdtdec_phandle_args args;
+       const char *phy_mode;
+       u32 phy_modereg;
        int nodes[2];   /* Max. two GMACs */
        int ret, count;
        int i, node;
@@ -132,11 +157,23 @@ int cpu_eth_init(bd_t *bis)
                        continue;
                }
 
-               dwmac_deassert_reset(args.args[0]);
+               phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+               ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+               if (ret) {
+                       debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+                       continue;
+               }
+
+               dwmac_deassert_reset(args.args[0], phy_modereg);
        }
 
        return 0;
 }
+#else
+static int socfpga_eth_reset(void)
+{
+       return 0;
+};
 #endif
 
 struct {
@@ -232,7 +269,7 @@ int arch_misc_init(void)
        setenv("bootmode", bsel_str[bsel].mode);
        if (fpga_id >= 0)
                setenv("fpgatype", socfpga_fpga_model[fpga_id].var);
-       return 0;
+       return socfpga_eth_reset();
 }
 #endif