Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6

[mv-sheeva.git] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index baf638487a2d530acaf30c7cab9581b3ec5b6f47..5bd7c89a604515273212ea304a02353ab9af5c39 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -399,7 +399,7 @@ config CPU_V6
 config CPU_32v6K
        bool "Support ARM V6K processor extensions" if !SMP
        depends on CPU_V6
-       default y if SMP && !ARCH_MX3
+       default y if SMP && !(ARCH_MX3 || ARCH_OMAP2)
        help
          Say Y here if your ARMv6 processor supports the 'K' extension.
          This enables the kernel to use some instructions not present
@@ -410,7 +410,7 @@ config CPU_32v6K
 # ARMv7
 config CPU_V7
        bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
-       select CPU_32v6K
+       select CPU_32v6K if !ARCH_OMAP2
        select CPU_32v7
        select CPU_ABRT_EV7
        select CPU_PABRT_V7
@@ -736,6 +736,12 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
 config OUTER_CACHE
        bool
 
+config OUTER_CACHE_SYNC
+       bool
+       help
+         The outer cache has a outer_cache_fns.sync function pointer
+         that can be used to drain the write buffer of the outer cache.
+
 config CACHE_FEROCEON_L2
        bool "Enable the Feroceon L2 cache controller"
        depends on ARCH_KIRKWOOD || ARCH_MV78XX0
@@ -754,9 +760,10 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"
        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-                  REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK
+                  REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
        default y
        select OUTER_CACHE
+       select OUTER_CACHE_SYNC
        help
          This option enables the L2x0 PrimeCell.
 
@@ -779,5 +786,11 @@ config CACHE_XSC3L2
 
 config ARM_L1_CACHE_SHIFT
        int
-       default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
+       default 6 if ARM_L1_CACHE_SHIFT_6
        default 5
+
+config ARCH_HAS_BARRIERS
+       bool
+       help
+         This option allows the use of custom mandatory barriers
+         included via the mach/barriers.h file.