Merge tag 'please-pull-getrandom' of git://git.kernel.org/pub/scm/linux/kernel/git...

[karo-tx-linux.git] / arch / arm / mm / proc-arm920.S

diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 549557df6d57a4273e99b2d0901b847af4382a39..22bf8dde4f84b331a07e740800785791dfb852f9 100644 (file)
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -63,7 +63,7 @@
  * cpu_arm920_proc_init()
  */
 ENTRY(cpu_arm920_proc_init)
-       mov     pc, lr
+       ret     lr
 
 /*
  * cpu_arm920_proc_fin()
@@ -73,7 +73,7 @@ ENTRY(cpu_arm920_proc_fin)
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       mov     pc, lr
+       ret     lr
 
 /*
  * cpu_arm920_reset(loc)
@@ -97,7 +97,7 @@ ENTRY(cpu_arm920_reset)
        bic     ip, ip, #0x000f                 @ ............wcam
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
-       mov     pc, r0
+       ret     r0
 ENDPROC(cpu_arm920_reset)
        .popsection
 
@@ -107,7 +107,7 @@ ENDPROC(cpu_arm920_reset)
        .align  5
 ENTRY(cpu_arm920_do_idle)
        mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
-       mov     pc, lr
+       ret     lr
 
 
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -120,7 +120,7 @@ ENTRY(cpu_arm920_do_idle)
 ENTRY(arm920_flush_icache_all)
        mov     r0, #0
        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
-       mov     pc, lr
+       ret     lr
 ENDPROC(arm920_flush_icache_all)
 
 /*
@@ -151,7 +151,7 @@ __flush_whole_cache:
        tst     r2, #VM_EXEC
        mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
        mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     flush_user_cache_range(start, end, flags)
@@ -177,7 +177,7 @@ ENTRY(arm920_flush_user_cache_range)
        blo     1b
        tst     r2, #VM_EXEC
        mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     coherent_kern_range(start, end)
@@ -211,7 +211,7 @@ ENTRY(arm920_coherent_user_range)
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     r0, #0
-       mov     pc, lr
+       ret     lr
 
 /*
  *     flush_kern_dcache_area(void *addr, size_t size)
@@ -231,7 +231,7 @@ ENTRY(arm920_flush_kern_dcache_area)
        mov     r0, #0
        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_inv_range(start, end)
@@ -257,7 +257,7 @@ arm920_dma_inv_range:
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_clean_range(start, end)
@@ -276,7 +276,7 @@ arm920_dma_clean_range:
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_flush_range(start, end)
@@ -293,7 +293,7 @@ ENTRY(arm920_dma_flush_range)
        cmp     r0, r1
        blo     1b
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
-       mov     pc, lr
+       ret     lr
 
 /*
  *     dma_map_area(start, size, dir)
@@ -316,7 +316,7 @@ ENDPROC(arm920_dma_map_area)
  *     - dir   - DMA direction
  */
 ENTRY(arm920_dma_unmap_area)
-       mov     pc, lr
+       ret     lr
 ENDPROC(arm920_dma_unmap_area)
 
        .globl  arm920_flush_kern_cache_louis
@@ -332,7 +332,7 @@ ENTRY(cpu_arm920_dcache_clean_area)
        add     r0, r0, #CACHE_DLINESIZE
        subs    r1, r1, #CACHE_DLINESIZE
        bhi     1b
-       mov     pc, lr
+       ret     lr
 
 /* =============================== PageTable ============================== */
 
@@ -367,7 +367,7 @@ ENTRY(cpu_arm920_switch_mm)
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 #endif
-       mov     pc, lr
+       ret     lr
 
 /*
  * cpu_arm920_set_pte(ptep, pte, ext)
@@ -382,7 +382,7 @@ ENTRY(cpu_arm920_set_pte_ext)
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 #endif
-       mov     pc, lr
+       ret     lr
 
 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
 .globl cpu_arm920_suspend_size
@@ -423,7 +423,7 @@ __arm920_setup:
        mrc     p15, 0, r0, c1, c0              @ get control register v4
        bic     r0, r0, r5
        orr     r0, r0, r6
-       mov     pc, lr
+       ret     lr
        .size   __arm920_setup, . - __arm920_setup
 
        /*