ENGR00177884-2 mx6q sabresd: config USB pin according to board

[karo-tx-linux.git] / arch / arm / plat-mxc / include / mach / iomux-mx6q.h

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
index ca94008e8e7634cb6c7933bd353767c7e09fd7af..ec6b2281e76ddeb7d6dfcebf38f3e0ecf0d8630a 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
@@ -58,6 +58,10 @@ typedef enum iomux_config {
                PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |        \
                PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 
+#define MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM (PAD_CTL_PKE | PAD_CTL_PUE |           \
+               PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
+               PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
 #define MX6Q_USDHC_PAD_CTRL_100MHZ     (PAD_CTL_PKE | PAD_CTL_PUE |    \
                PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED |        \
                PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -70,6 +74,10 @@ typedef enum iomux_config {
                PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |       \
                PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
+#define MX6Q_GPIO_16_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |    \
+               PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED  |    \
+               PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
 #define MX6Q_DISP_PAD_CLT      MX6Q_HIGH_DRV
 
 #define MX6Q_I2C_PAD_CTRL      (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
@@ -1623,6 +1631,8 @@ typedef enum iomux_config {
 #define _MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH         \
                IOMUX_PAD(0x04E8, 0x01D4, 7, 0x0000, 0, 0)
 
+#define _MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID                                 \
+               IOMUX_PAD(0x04EC, 0x01D8, 0, 0x0000, 0, 0)
 #define _MX6Q_PAD_ENET_RX_ER__ENET_RX_ER                               \
                IOMUX_PAD(0x04EC, 0x01D8, 1, 0x0000, 0, 0)
 #define _MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR                               \
@@ -2429,7 +2439,7 @@ typedef enum iomux_config {
 #define _MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN         \
                IOMUX_PAD(0x0618, 0x0248, 1, 0x0000, 0, 0)
 #define _MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT                \
-               IOMUX_PAD(0x0618, 0x0248, 2, 0x083C, 1, 0)
+               IOMUX_PAD(0x0618, 0x0248, 0x12, 0x083C, 1, 0)
 #define _MX6Q_PAD_GPIO_16__USDHC1_LCTL                 \
                IOMUX_PAD(0x0618, 0x0248, 3, 0x0000, 0, 0)
 #define _MX6Q_PAD_GPIO_16__SPDIF_IN1                   \
@@ -5227,6 +5237,8 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH         \
                (_MX6Q_PAD_ENET_REF_CLK__ANATOP_USBPHY1_TSTO_RX_SQUELCH | MUX_PAD_CTRL(NO_PAD_CTRL))
 
+#define  MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID \
+               (_MX6Q_PAD_ENET_RX_ER__ANATOP_USBOTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_RX_ER__ENET_RX_ER               \
                (_MX6Q_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR               \
@@ -6032,7 +6044,8 @@ typedef enum iomux_config {
 #define  MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN         \
                (_MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT                \
-               (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
+               (_MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT | \
+               MUX_PAD_CTRL(MX6Q_GPIO_16_PAD_CTRL))
 #define  MX6Q_PAD_GPIO_16__USDHC1_LCTL         \
                (_MX6Q_PAD_GPIO_16__USDHC1_LCTL | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
 #define  MX6Q_PAD_GPIO_16__SPDIF_IN1           \
@@ -7220,6 +7233,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_DAT1__USDHC1_DAT1                \
                (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM            \
+               (_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_DAT1__ECSPI5_SS0         \
                (_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_DAT1__PWM3_PWMO          \
@@ -7237,6 +7252,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_DAT0__USDHC1_DAT0                \
                (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM            \
+               (_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_DAT0__ECSPI5_MISO                \
                (_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS           \
@@ -7254,6 +7271,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_DAT3__USDHC1_DAT3                \
                (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM            \
+               (_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_DAT3__ECSPI5_SS2         \
                (_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3                \
@@ -7271,6 +7290,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_CMD__USDHC1_CMD          \
                (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM              \
+               (_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_CMD__ECSPI5_MOSI         \
                (_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_CMD__PWM4_PWMO           \
@@ -7284,6 +7305,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_DAT2__USDHC1_DAT2                \
                (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM            \
+               (_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_DAT2__ECSPI5_SS1         \
                (_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2                \
@@ -7301,6 +7324,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_CLK__USDHC1_CLK          \
                (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM              \
+               (_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_CLK__ECSPI5_SCLK         \
                (_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT              \