arm: plat-omap: Cleanup irq_desc access

[mv-sheeva.git] / arch / arm / plat-omap / gpio.c

diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 971d186369423c7eacb03e580a74714ad35e6f26..af07333e478e3c39c29f91d65c20715d6e47f0ac 100644 (file)
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -755,12 +755,6 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
        bank = irq_data_get_irq_chip_data(d);
        spin_lock_irqsave(&bank->lock, flags);
        retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
-       if (retval == 0) {
-               struct irq_desc *desc = irq_to_desc(d->irq);
-
-               desc->status &= ~IRQ_TYPE_SENSE_MASK;
-               desc->status |= type;
-       }
        spin_unlock_irqrestore(&bank->lock, flags);
 
        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
@@ -1270,8 +1264,7 @@ static void gpio_unmask_irq(struct irq_data *d)
        unsigned int gpio = d->irq - IH_GPIO_BASE;
        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
        unsigned int irq_mask = 1 << get_gpio_index(gpio);
-       struct irq_desc *desc = irq_to_desc(d->irq);
-       u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
+       u32 trigger = irqd_get_trigger_type(d);
 
        if (trigger)
                _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
@@ -1672,9 +1665,7 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank)
 
        for (j = bank->virtual_irq_start;
                     j < bank->virtual_irq_start + bank_width; j++) {
-               struct irq_desc *d = irq_to_desc(j);
-
-               lockdep_set_class(&d->lock, &gpio_lock_class);
+               irq_set_lockdep_class(j, &gpio_lock_class);
                set_irq_chip_data(j, bank);
                if (bank_is_mpuio(bank))
                        set_irq_chip(j, &mpuio_irq_chip);