x86: make 64 bit to use default_inquire_remote_apic

[mv-sheeva.git] / arch / blackfin / Kconfig

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 8f1f97d56e1ecfec191b185350e7f374cd0df00b..3640cdc38aace3db670bbd703eb31959bd76cf05 100644 (file)
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -777,7 +777,7 @@ config CACHELINE_ALIGNED_L1
        default n if BF54x
        depends on !BF531
        help
-         If enabled, cacheline_anligned data is linked
+         If enabled, cacheline_aligned data is linked
          into L1 data memory. (less latency)
 
 config SYSCALL_TAB_L1
@@ -957,7 +957,7 @@ config MPU
          memory they do not own.  This comes at a performance penalty
          and is recommended only for debugging.
 
-comment "Asynchonous Memory Configuration"
+comment "Asynchronous Memory Configuration"
 
 menu "EBIU_AMGCTL Global Control"
 config C_AMCKEN
@@ -989,7 +989,7 @@ config C_B3PEN
        default n
 
 choice
-       prompt"Enable Asynchonous Memory Banks"
+       prompt "Enable Asynchronous Memory Banks"
        default C_AMBEN_ALL
 
 config C_AMBEN
@@ -1129,6 +1129,7 @@ endchoice
 
 config PM_WAKEUP_BY_GPIO
        bool "Allow Wakeup from Standby by GPIO"
+       depends on PM && !BF54x
 
 config PM_WAKEUP_GPIO_NUMBER
        int "GPIO number"
@@ -1168,6 +1169,12 @@ config PM_BFIN_WAKE_GP
        default n
        help
          Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
+         (all processors, except ADSP-BF549). This option sets
+         the general-purpose wake-up enable (GPWE) control bit to enable
+         wake-up upon detection of an active low signal on the /GPW (PH7) pin.
+         On ADSP-BF549 this option enables the the same functionality on the
+         /MRXON pin also PH7.
+
 endmenu
 
 menu "CPU Frequency scaling"