#include <asm/mach-common/bits/watchdog.h>
#include <asm/mach-common/bits/bootrom.h>
#include <asm/mach-common/bits/core.h>
-
-#define BUG() while (1) { asm volatile("emuexcpt;"); }
-
-#include "serial.h"
+#include <asm/serial.h>
#ifndef __ADSPBF60x__
#include <asm/mach-common/bits/ebiu.h>
__attribute__((always_inline))
static inline void serial_init(void)
{
- uint32_t uart_base = UART_BASE;
-
#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
# ifdef BFIN_BOOT_UART_USE_RTS
# define BFIN_UART_USE_RTS 1
# define BFIN_UART_USE_RTS 0
# endif
if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
+ uint32_t uart_base = UART_BASE;
size_t i;
/* force RTS rather than relying on auto RTS */
#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
if (BFIN_DEBUG_EARLY_SERIAL) {
- serial_early_init(uart_base);
- serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
+ serial_early_init(UART_BASE);
+ serial_early_set_baud(UART_BASE, CONFIG_BAUDRATE);
}
#endif
}
if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
serial_putc('e');
#ifdef __ADSPBF60x__
+ /* Reset system event controller */
bfin_write_SEC_GCTL(0x2);
+ bfin_write_SEC_CCTL(0x2);
SSYNC();
+
+ /* Enable fault event input and system reset action in fault
+ * controller. Route watchdog timeout event to fault interface.
+ */
bfin_write_SEC_FCTL(0xc1);
+ /* Enable watchdog interrupt source */
bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
-
- bfin_write_SEC_CCTL(0x2);
SSYNC();
+
+ /* Enable system event controller */
bfin_write_SEC_GCTL(0x1);
bfin_write_SEC_CCTL(0x1);
+ SSYNC();
#endif
bfin_write_WDOG_CTL(WDDIS);
SSYNC();
__attribute__((always_inline)) static inline u16
program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
{
- u16 vr_ctl;
+ u16 vr_ctl = 0;
serial_putc('a');
serial_putc('a');
+ if (BFIN_DEBUG_EARLY_SERIAL ||
+ CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
#ifdef __ADSPBF60x__
sdivR = bfin_read_CGU_DIV();
sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
divisor = vcoB * sdivR;
quotient = early_division(dividend, divisor);
serial_early_put_div(quotient - ANOMALY_05000230);
+ }
+
serial_putc('c');
}
continue;
serial_putc('z');
- uint32_t *hibernate_magic = bfin_read32(DPM0_RESTORE4);
+ uint32_t *hibernate_magic =
+ (uint32_t *)bfin_read32(DPM0_RESTORE4);
SSYNC(); /* make sure memory controller is done */
if (hibernate_magic[0] == 0xDEADBEEF) {
serial_putc('c');
uint32_t *hibernate_magic = 0;
SSYNC();
+ /* cppcheck-suppress nullPointer */
if (hibernate_magic[0] == 0xDEADBEEF) {
serial_putc('c');
bfin_write_EVT15(hibernate_magic[1]);