w[p2] = r0;
ssync;
+ p2.h = hi(EBIU_MBSCTL);
+ p2.l = lo(EBIU_MBSCTL);
+ r0.h = hi(CONFIG_EBIU_MBSCTLVAL);
+ r0.l = lo(CONFIG_EBIU_MBSCTLVAL);
+ [p2] = r0;
+ ssync;
+
+ p2.h = hi(EBIU_MODE);
+ p2.l = lo(EBIU_MODE);
+ r0.h = hi(CONFIG_EBIU_MODEVAL);
+ r0.l = lo(CONFIG_EBIU_MODEVAL);
+ [p2] = r0;
+ ssync;
+
+ p2.h = hi(EBIU_FCTL);
+ p2.l = lo(EBIU_FCTL);
+ r0.h = hi(CONFIG_EBIU_FCTLVAL);
+ r0.l = lo(CONFIG_EBIU_FCTLVAL);
+ [p2] = r0;
+ ssync;
+
/* This section keeps the processor in supervisor mode
* during kernel boot. Switches to user mode at end of boot.
* See page 3-9 of Hardware Reference manual for documentation.
w[p0] = r0.l;
ssync;
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
+ p0.h = hi(SIC_IWR0);
+ p0.l = lo(SIC_IWR0);
r0.l = 0x1;
r0.h = 0x0;
[p0] = r0;
[P2] = R1;
SSYNC;
- p0.h = hi(SIC_IWR);
- p0.l = lo(SIC_IWR);
+ p0.h = hi(SIC_IWR0);
+ p0.l = lo(SIC_IWR0);
r0.l = lo(IWR_ENABLE_ALL);
r0.h = hi(IWR_ENABLE_ALL);
[p0] = r0;