Blackfin: bf561: update a few more SIC_SYSCR locations

[mv-sheeva.git] / arch / blackfin / mach-bf561 / smp.c

diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index f540ed1257d6bc707cf8bc3c8a20a5f9e3e41c74..be6083a7e42fe317045d324734d20b08b15338e2 100644 (file)
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
 
        spin_lock(&boot_lock);
 
-       if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) {
+       if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
                /* CoreB already running, sending ipi to wakeup it */
                platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
        } else {
                /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
-               bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT);
+               bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
                SSYNC();
        }