IPVS: Rename ip_vs_proto_ah.c to ip_vs_proto_ah_esp.c

[mv-sheeva.git] / arch / blackfin / mach-common / cacheinit.S

diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S
index 7924a90d9658ef900d04aa390ec9f13a514b68fb..22fada0c1cb3e0e16a27039dda9648080fd3c63b 100644 (file)
--- a/arch/blackfin/mach-common/cacheinit.S
+++ b/arch/blackfin/mach-common/cacheinit.S
@@ -38,104 +38,40 @@
 
 .text
 
-#if defined(CONFIG_BLKFIN_CACHE)
-ENTRY(_bfin_icache_init)
+#if ANOMALY_05000125
+#if defined(CONFIG_BFIN_ICACHE)
+ENTRY(_bfin_write_IMEM_CONTROL)
 
-       /* Initialize Instruction CPLBS */
-
-       I0.L = (ICPLB_ADDR0 & 0xFFFF);
-       I0.H = (ICPLB_ADDR0 >> 16);
-
-       I1.L = (ICPLB_DATA0 & 0xFFFF);
-       I1.H = (ICPLB_DATA0 >> 16);
-
-       I2.L = _icplb_table;
-       I2.H = _icplb_table;
-
-       r1 = -1;        /* end point comparison */
-       r3 = 15;        /* max counter */
-
-/* read entries from table */
-
-.Lread_iaddr:
-       R0 = [I2++];
-       CC = R0 == R1;
-       IF CC JUMP .Lidone;
-       [I0++] = R0;
-
-.Lread_idata:
-       R2 = [I2++];
-       [I1++] = R2;
-       R3 = R3 + R1;
-       CC = R3 == R1;
-       IF !CC JUMP .Lread_iaddr;
-
-.Lidone:
        /* Enable Instruction Cache */
-       P0.l = (IMEM_CONTROL & 0xFFFF);
-       P0.h = (IMEM_CONTROL >> 16);
-       R1 = [P0];
-       R0 = (IMC | ENICPLB);
-       R0 = R0 | R1;
+       P0.l = LO(IMEM_CONTROL);
+       P0.h = HI(IMEM_CONTROL);
 
        /* Anomaly 05000125 */
-       CLI R2;
+       CLI R1;
        SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
        .align 8;
        [P0] = R0;
        SSYNC;
-       STI R2;
+       STI R1;
        RTS;
 
-ENDPROC(_bfin_icache_init)
+ENDPROC(_bfin_write_IMEM_CONTROL)
 #endif
 
-#if defined(CONFIG_BLKFIN_DCACHE)
-ENTRY(_bfin_dcache_init)
-
-       /* Initialize Data CPLBS */
-
-       I0.L = (DCPLB_ADDR0 & 0xFFFF);
-       I0.H = (DCPLB_ADDR0 >> 16);
+#if defined(CONFIG_BFIN_DCACHE)
+ENTRY(_bfin_write_DMEM_CONTROL)
+       P0.l = LO(DMEM_CONTROL);
+       P0.h = HI(DMEM_CONTROL);
 
-       I1.L = (DCPLB_DATA0 & 0xFFFF);
-       I1.H = (DCPLB_DATA0 >> 16);
-
-       I2.L = _dcplb_table;
-       I2.H = _dcplb_table;
-
-       R1 = -1;        /* end point comparison */
-       R3 = 15;        /* max counter */
-
-       /* read entries from table */
-.Lread_daddr:
-       R0 = [I2++];
-       cc = R0 == R1;
-       IF CC JUMP .Lddone;
-       [I0++] = R0;
-
-.Lread_ddata:
-       R2 = [I2++];
-       [I1++] = R2;
-       R3 = R3 + R1;
-       CC = R3 == R1;
-       IF !CC JUMP .Lread_daddr;
-.Lddone:
-       P0.L = (DMEM_CONTROL & 0xFFFF);
-       P0.H = (DMEM_CONTROL >> 16);
-       R1 = [P0];
-
-       R0 = DMEM_CNTR;
-
-       R0 = R0 | R1;
-       /* Anomaly 05000125 */
-       CLI R2;
+       CLI R1;
        SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
        .align 8;
        [P0] = R0;
        SSYNC;
-       STI R2;
+       STI R1;
        RTS;
 
-ENDPROC(_bfin_dcache_init)
+ENDPROC(_bfin_write_DMEM_CONTROL)
+#endif
+
 #endif