[Blackfin] arch: Fix bug to Enable kernel to build for bf548 with PM.

[karo-tx-linux.git] / arch / blackfin / mach-common / dpmc.S

diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
index 97cdcd6a00d47b8c52eaaee3f71c2bb9e155bd16..301ac1b6681f9b938e5001e20a9283dafbce11e3 100644 (file)
--- a/arch/blackfin/mach-common/dpmc.S
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -38,9 +38,12 @@ ENTRY(_unmask_wdog_wakeup_evt)
 #if defined(CONFIG_BF561)
        P0.H = hi(SICA_IWR1);
        P0.L = lo(SICA_IWR1);
+#elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+       P0.h = HI(SIC_IWR0);
+       P0.l = LO(SIC_IWR0);
 #else
-       P0.h = (SIC_IWR >> 16);
-       P0.l = (SIC_IWR & 0xFFFF);
+       P0.h = HI(SIC_IWR);
+       P0.l = LO(SIC_IWR);
 #endif
        R7 = [P0];
 #if defined(CONFIG_BF561)
@@ -60,11 +63,11 @@ ENTRY(_unmask_wdog_wakeup_evt)
         */
        R7 = 0x0000(z);
 #if defined(CONFIG_BF561)
-       P0.h = (WDOGA_STAT >> 16);
-       P0.l = (WDOGA_STAT & 0xFFFF);
+       P0.h = HI(WDOGA_STAT);
+       P0.l = LO(WDOGA_STAT);
 #else
-       P0.h = (WDOG_STAT >> 16);
-       P0.l = (WDOG_STAT & 0xFFFF);
+       P0.h = HI(WDOG_STAT);
+       P0.l = LO(WDOG_STAT);
 #endif
        [P0] = R7;
        SSYNC;
@@ -73,21 +76,21 @@ ENTRY(_unmask_wdog_wakeup_evt)
 ENTRY(_program_wdog_timer)
        [--SP] = ( R7:0, P5:0 );
 #if defined(CONFIG_BF561)
-       P0.h = (WDOGA_CNT >> 16);
-       P0.l = (WDOGA_CNT & 0xFFFF);
+       P0.h = HI(WDOGA_CNT);
+       P0.l = LO(WDOGA_CNT);
 #else
-       P0.h = (WDOG_CNT >> 16);
-       P0.l = (WDOG_CNT & 0xFFFF);
+       P0.h = HI(WDOG_CNT);
+       P0.l = LO(WDOG_CNT);
 #endif
        [P0] = R0;
        SSYNC;
 
 #if defined(CONFIG_BF561)
-       P0.h = (WDOGA_CTL >> 16);
-       P0.l = (WDOGA_CTL & 0xFFFF);
+       P0.h = HI(WDOGA_CTL);
+       P0.l = LO(WDOGA_CTL);
 #else
-       P0.h = (WDOG_CTL >> 16);
-       P0.l = (WDOG_CTL & 0xFFFF);
+       P0.h = HI(WDOG_CTL);
+       P0.l = LO(WDOG_CTL);
 #endif
        R7 = W[P0](Z);
        CC = BITTST(R7,1);
@@ -97,11 +100,11 @@ ENTRY(_program_wdog_timer)
 
 .LSKIP_WRITE_TO_STAT:
 #if defined(CONFIG_BF561)
-       P0.h = (WDOGA_CTL >> 16);
-           P0.l = (WDOGA_CTL & 0xFFFF);
+       P0.h = HI(WDOGA_CTL);
+       P0.l = LO(WDOGA_CTL);
 #else
-       P0.h = (WDOG_CTL >> 16);
-           P0.l = (WDOG_CTL & 0xFFFF);
+       P0.h = HI(WDOG_CTL);
+       P0.l = LO(WDOG_CTL);
 #endif
        R7 = W[P0](Z);
        BITCLR(R7,1);   /* Enable GP event */
@@ -122,11 +125,11 @@ ENTRY(_clear_wdog_wakeup_evt)
        [--SP] = ( R7:0, P5:0 );
 
 #if defined(CONFIG_BF561)
-       P0.h = (WDOGA_CTL >> 16);
-       P0.l = (WDOGA_CTL & 0xFFFF);
+       P0.h = HI(WDOGA_CTL);
+       P0.l = LO(WDOGA_CTL);
 #else
-       P0.h = (WDOG_CTL >> 16);
-       P0.l = (WDOG_CTL & 0xFFFF);
+       P0.h = HI(WDOG_CTL);
+       P0.l = LO(WDOG_CTL);
 #endif
        R7 = 0x0AD6(Z);
        W[P0] = R7.L;
@@ -149,11 +152,11 @@ ENTRY(_clear_wdog_wakeup_evt)
 ENTRY(_disable_wdog_timer)
        [--SP] = ( R7:0, P5:0 );
 #if defined(CONFIG_BF561)
-       P0.h = (WDOGA_CTL >> 16);
-       P0.l = (WDOGA_CTL & 0xFFFF);
+       P0.h = HI(WDOGA_CTL);
+       P0.l = LO(WDOGA_CTL);
 #else
-       P0.h = (WDOG_CTL >> 16);
-       P0.l = (WDOG_CTL & 0xFFFF);
+       P0.h = HI(WDOG_CTL);
+       P0.l = LO(WDOG_CTL);
 #endif
        R7 = 0xAD6(Z);
        W[P0] = R7.L;
@@ -236,7 +239,7 @@ ENTRY(_deep_sleep)
 
        call _set_sic_iwr;
 
-       call _set_sdram_srfs;
+       call _set_dram_srfs;
 
        /* Clear all the interrupts,bits sticky */
        R0 = 0xFFFF (Z);
@@ -253,7 +256,7 @@ ENTRY(_deep_sleep)
        SSYNC;
        IDLE;
 
-       call _unset_sdram_srfs;
+       call _unset_dram_srfs;
 
        call _test_pll_locked;
 
@@ -285,7 +288,7 @@ ENTRY(_sleep_deeper)
        P3 = R0;
        R0 = IWR_ENABLE(0);
        call _set_sic_iwr;
-       call _set_sdram_srfs;
+       call _set_dram_srfs;
 
        /* Clear all the interrupts,bits sticky */
        R0 = 0xFFFF (Z);
@@ -300,7 +303,7 @@ ENTRY(_sleep_deeper)
        P0.H = hi(PLL_CTL);
        P0.L = lo(PLL_CTL);
        R5 = W[P0](z);
-       R0.L = (MIN_VC/CONFIG_CLKIN_HZ) << 9;
+       R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
        W[P0] = R0.l;
 
        SSYNC;
@@ -360,7 +363,7 @@ ENTRY(_sleep_deeper)
        IDLE;
        call _test_pll_locked;
 
-       call _unset_sdram_srfs;
+       call _unset_dram_srfs;
 
        STI R4;
 
@@ -368,25 +371,47 @@ ENTRY(_sleep_deeper)
        ( R7:0, P5:0 ) = [SP++];
        RTS;
 
-ENTRY(_set_sdram_srfs)
-       /*  set the sdram to self refresh mode */
+ENTRY(_set_dram_srfs)
+       /*  set the dram to self refresh mode */
+#if defined(CONFIG_BF54x)
+       P0.H = hi(EBIU_RSTCTL);
+       P0.L = lo(EBIU_RSTCTL);
+       R2 = [P0];
+       R3.H = hi(SRREQ);
+       R3.L = lo(SRREQ);
+#else
        P0.H = hi(EBIU_SDGCTL);
        P0.L = lo(EBIU_SDGCTL);
        R2 = [P0];
        R3.H = hi(SRFS);
        R3.L = lo(SRFS);
+#endif
        R2 = R2|R3;
        [P0] = R2;
        ssync;
+#if defined(CONFIG_BF54x)
+.LSRR_MODE:
+       R2 = [P0];
+       CC = BITTST(R2, 4);
+       if !CC JUMP .LSRR_MODE;
+#endif
        RTS;
 
-ENTRY(_unset_sdram_srfs)
-       /*  set the sdram out of self refresh mode */
+ENTRY(_unset_dram_srfs)
+       /*  set the dram out of self refresh mode */
+#if defined(CONFIG_BF54x)
+       P0.H = hi(EBIU_RSTCTL);
+       P0.L = lo(EBIU_RSTCTL);
+       R2 = [P0];
+       R3.H = hi(SRREQ);
+       R3.L = lo(SRREQ);
+#else
        P0.H = hi(EBIU_SDGCTL);
        P0.L = lo(EBIU_SDGCTL);
        R2 = [P0];
        R3.H = hi(SRFS);
        R3.L = lo(SRFS);
+#endif
        R3 = ~R3;
        R2 = R2&R3;
        [P0] = R2;
@@ -394,8 +419,13 @@ ENTRY(_unset_sdram_srfs)
        RTS;
 
 ENTRY(_set_sic_iwr)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+       P0.H = hi(SIC_IWR0);
+       P0.L = lo(SIC_IWR0);
+#else
        P0.H = hi(SIC_IWR);
        P0.L = lo(SIC_IWR);
+#endif
        [P0] = R0;
        SSYNC;
        RTS;