Blackfin: cleanup sync handling when enabling/disabling cplbs

[mv-sheeva.git] / arch / blackfin / mach-common / entry.S

diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 4e8e3fe0ba1c14f7e415f0e6ca0e0e1e1ff744ff..e7eb16355f74c4f124a28c53acbaf1f1af8a4d5a 100644 (file)
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -397,8 +397,7 @@ ENTRY(_double_fault)
 
        R5 = [P4];              /* Control Register*/
        BITCLR(R5,ENICPLB_P);
-       SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
-       .align 8;
+       CSYNC;          /* Disabling of CPLBs should be proceeded by a CSYNC */
        [P4] = R5;
        SSYNC;
 
@@ -406,8 +405,7 @@ ENTRY(_double_fault)
        P4.H = HI(DMEM_CONTROL);
        R5 = [P4];
        BITCLR(R5,ENDCPLB_P);
-       SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
-       .align 8;
+       CSYNC;          /* Disabling of CPLBs should be proceeded by a CSYNC */
        [P4] = R5;
        SSYNC;
 
@@ -1146,9 +1144,7 @@ ENTRY(_early_trap)
 
        R5 = [P4];              /* Control Register*/
        BITCLR(R5,ENICPLB_P);
-       CLI R1;
-       SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
-       .align 8;
+       CSYNC;          /* Disabling of CPLBs should be proceeded by a CSYNC */
        [P4] = R5;
        SSYNC;
 
@@ -1156,11 +1152,9 @@ ENTRY(_early_trap)
        P4.H = HI(DMEM_CONTROL);
        R5 = [P4];
        BITCLR(R5,ENDCPLB_P);
-       SSYNC;          /* SSYNC required before writing to DMEM_CONTROL. */
-       .align 8;
+       CSYNC;          /* Disabling of CPLBs should be proceeded by a CSYNC */
        [P4] = R5;
        SSYNC;
-       STI R1;
 
        r0 = sp;        /* stack frame pt_regs pointer argument ==> r0 */
        r1 = RETX;