/*
* Build the IRQ handler stubs using macros from irq.h.
*/
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+BUILD_TIMER_IRQ(0x31, 0)
+#else
BUILD_IRQ(0x31)
+#endif
BUILD_IRQ(0x32)
BUILD_IRQ(0x33)
BUILD_IRQ(0x34)
BUILD_IRQ(0x48)
BUILD_IRQ(0x49)
BUILD_IRQ(0x4a)
+#ifdef CONFIG_ETRAXFS
+BUILD_TIMER_IRQ(0x4b, 0)
+#else
BUILD_IRQ(0x4b)
+#endif
BUILD_IRQ(0x4c)
BUILD_IRQ(0x4d)
BUILD_IRQ(0x4e)
unsigned long flags;
spin_lock_irqsave(&irq_lock, flags);
- if (irq - FIRST_IRQ < 32)
+ /* Remember, 1 let thru, 0 block. */
+ if (irq - FIRST_IRQ < 32) {
intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
rw_mask, 0);
- else
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 1);
-
- /* Remember; 1 let thru, 0 block. */
- if (irq - FIRST_IRQ < 32)
intr_mask &= ~(1 << (irq - FIRST_IRQ));
- else
- intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
-
- if (irq - FIRST_IRQ < 32)
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
0, intr_mask);
- else
+ } else {
+ intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
+ rw_mask, 1);
+ intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
1, intr_mask);
+ }
spin_unlock_irqrestore(&irq_lock, flags);
}
unsigned long flags;
spin_lock_irqsave(&irq_lock, flags);
- if (irq - FIRST_IRQ < 32)
+ /* Remember, 1 let thru, 0 block. */
+ if (irq - FIRST_IRQ < 32) {
intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
rw_mask, 0);
- else
- intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
- rw_mask, 1);
-
- /* Remember; 1 let thru, 0 block. */
- if (irq - FIRST_IRQ < 32)
intr_mask |= (1 << (irq - FIRST_IRQ));
- else
- intr_mask |= (1 << (irq - FIRST_IRQ - 32));
-
- if (irq - FIRST_IRQ < 32)
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
0, intr_mask);
- else
+ } else {
+ intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
+ rw_mask, 1);
+ intr_mask |= (1 << (irq - FIRST_IRQ - 32));
REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
1, intr_mask);
-
+ }
spin_unlock_irqrestore(&irq_lock, flags);
}
}
-static unsigned int startup_crisv32_irq(unsigned int irq)
-{
- crisv32_unmask_irq(irq);
- return 0;
-}
-
-static void shutdown_crisv32_irq(unsigned int irq)
+static void enable_crisv32_irq(struct irq_data *data)
{
- crisv32_mask_irq(irq);
+ crisv32_unmask_irq(data->irq);
}
-static void enable_crisv32_irq(unsigned int irq)
+static void disable_crisv32_irq(struct irq_data *data)
{
- crisv32_unmask_irq(irq);
+ crisv32_mask_irq(data->irq);
}
-static void disable_crisv32_irq(unsigned int irq)
-{
- crisv32_mask_irq(irq);
-}
-
-static void ack_crisv32_irq(unsigned int irq)
-{
-}
-
-static void end_crisv32_irq(unsigned int irq)
-{
-}
-
-int set_affinity_crisv32_irq(unsigned int irq, const struct cpumask *dest)
+static int set_affinity_crisv32_irq(struct irq_data *data,
+ const struct cpumask *dest, bool force)
{
unsigned long flags;
+
spin_lock_irqsave(&irq_lock, flags);
- irq_allocations[irq - FIRST_IRQ].mask = *dest;
+ irq_allocations[data->irq - FIRST_IRQ].mask = *dest;
spin_unlock_irqrestore(&irq_lock, flags);
-
return 0;
}
static struct irq_chip crisv32_irq_type = {
- .name = "CRISv32",
- .startup = startup_crisv32_irq,
- .shutdown = shutdown_crisv32_irq,
- .enable = enable_crisv32_irq,
- .disable = disable_crisv32_irq,
- .ack = ack_crisv32_irq,
- .end = end_crisv32_irq,
- .set_affinity = set_affinity_crisv32_irq
+ .name = "CRISv32",
+ .irq_shutdown = disable_crisv32_irq,
+ .irq_enable = enable_crisv32_irq,
+ .irq_disable = disable_crisv32_irq,
+ .irq_set_affinity = set_affinity_crisv32_irq,
};
void
/* Point all IRQ's to bad handlers. */
for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
- irq_desc[j].chip = &crisv32_irq_type;
+ set_irq_chip_and_handler(j, &crisv32_irq_type,
+ handle_simple_irq);
set_exception_vector(i, interrupt[j]);
}