MIPS: Add support for uncached accelerated mappings.

[mv-sheeva.git] / arch / mips / Kconfig

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index fd7620f025fab0ab25bcd9bca3e3dbf00b78161d..e2116b1f968ebc336e5b58345eace294f77b47c0 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -7,7 +7,7 @@ config MIPS
        select HAVE_ARCH_KGDB
        # Horrible source of confusion.  Die, die, die ...
        select EMBEDDED
-       select RTC_LIB if !LEMOTE_FULOONG2E
+       select RTC_LIB if !MACH_LOONGSON
 
 mainmenu "Linux/MIPS Kernel Configuration"
 
@@ -22,6 +22,7 @@ choice
 
 config MACH_ALCHEMY
        bool "Alchemy processor based machines"
+       select SYS_SUPPORTS_ZBOOT
 
 config AR7
        bool "Texas Instruments AR7"
@@ -36,6 +37,7 @@ config AR7
        select SYS_HAS_EARLY_PRINTK
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_LITTLE_ENDIAN
+       select SYS_SUPPORTS_ZBOOT_UART16550
        select GENERIC_GPIO
        select GCD
        select VLYNQ
@@ -192,6 +194,7 @@ config LASAT
 
 config MACH_LOONGSON
        bool "Loongson family of machines"
+       select SYS_SUPPORTS_ZBOOT_UART16550
        help
          This enables the support of Loongson family of machines.
 
@@ -233,6 +236,7 @@ config MIPS_MALTA
        select SYS_SUPPORTS_MIPS_CMP
        select SYS_SUPPORTS_MULTITHREADING
        select SYS_SUPPORTS_SMARTMIPS
+       select SYS_SUPPORTS_ZBOOT
        help
          This enables support for the MIPS Technologies Malta evaluation
          board.
@@ -1069,6 +1073,21 @@ config CPU_LOONGSON2E
          The Loongson 2E processor implements the MIPS III instruction set
          with many extensions.
 
+         It has an internal FPGA northbridge, which is compatiable to
+         bonito64.
+
+config CPU_LOONGSON2F
+       bool "Loongson 2F"
+       depends on SYS_HAS_CPU_LOONGSON2F
+       select CPU_LOONGSON2
+       help
+         The Loongson 2F processor implements the MIPS III instruction set
+         with many extensions.
+
+         Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
+         have a similar programming interface with FPGA northbridge used in
+         Loongson2E.
+
 config CPU_MIPS32_R1
        bool "MIPS32 Release 1"
        depends on SYS_HAS_CPU_MIPS32_R1
@@ -1294,6 +1313,16 @@ config CPU_CAVIUM_OCTEON
 
 endchoice
 
+config SYS_SUPPORTS_ZBOOT
+       bool
+       select HAVE_KERNEL_GZIP
+       select HAVE_KERNEL_BZIP2
+       select HAVE_KERNEL_LZMA
+
+config SYS_SUPPORTS_ZBOOT_UART16550
+       bool
+       select SYS_SUPPORTS_ZBOOT
+
 config CPU_LOONGSON2
        bool
        select CPU_SUPPORTS_32BIT_KERNEL
@@ -1303,6 +1332,12 @@ config CPU_LOONGSON2
 config SYS_HAS_CPU_LOONGSON2E
        bool
 
+config SYS_HAS_CPU_LOONGSON2F
+       bool
+       select CPU_SUPPORTS_CPUFREQ
+       select CPU_SUPPORTS_ADDRWINCFG if 64BIT
+       select CPU_SUPPORTS_UNCACHED_ACCELERATED
+
 config SYS_HAS_CPU_MIPS32_R1
        bool
 
@@ -1411,8 +1446,17 @@ config CPU_SUPPORTS_32BIT_KERNEL
        bool
 config CPU_SUPPORTS_64BIT_KERNEL
        bool
+config CPU_SUPPORTS_CPUFREQ
+       bool
+config CPU_SUPPORTS_ADDRWINCFG
+       bool
 config CPU_SUPPORTS_HUGEPAGES
        bool
+config CPU_SUPPORTS_UNCACHED_ACCELERATED
+       bool
+config MIPS_PGD_C0_CONTEXT
+       bool
+       default y if 64BIT && CPU_MIPSR2
 
 #
 # Set to y for ptrace access to watch registers.
@@ -2024,15 +2068,6 @@ config STACKTRACE_SUPPORT
 
 source "init/Kconfig"
 
-config PROBE_INITRD_HEADER
-       bool "Probe initrd header created by addinitrd"
-       depends on BLK_DEV_INITRD
-       help
-         Probe initrd header at the last page of kernel image.
-         Say Y here if you are using arch/mips/boot/addinitrd.c to
-         add initrd or initramfs image to the kernel image.
-         Otherwise, say N.
-
 source "kernel/Kconfig.freezer"
 
 menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"