MIPS: Define & use CP0_EBase bit definitions

[karo-tx-linux.git] / arch / mips / include / asm / mipsregs.h

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 3ad19ad04d8a282179423e9fcc5ecbb5557d26c7..57d72f2bf7450f054b4e3d3ccdbb1247a67e14bb 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -229,6 +229,8 @@
 
 /* MIPS32/64 EntryHI bit definitions */
 #define MIPS_ENTRYHI_EHINV     (_ULCAST_(1) << 10)
+#define MIPS_ENTRYHI_ASIDX     (_ULCAST_(0x3) << 8)
+#define MIPS_ENTRYHI_ASID      (_ULCAST_(0xff) << 0)
 
 /*
  * R4x00 interrupt enable / cause bits
@@ -390,6 +392,8 @@
 #define         CAUSEF_IP7             (_ULCAST_(1)   << 15)
 #define CAUSEB_FDCI            21
 #define CAUSEF_FDCI            (_ULCAST_(1)   << 21)
+#define CAUSEB_WP              22
+#define CAUSEF_WP              (_ULCAST_(1)   << 22)
 #define CAUSEB_IV              23
 #define CAUSEF_IV              (_ULCAST_(1)   << 23)
 #define CAUSEB_PCI             26
@@ -623,6 +627,7 @@
 #define MIPS_CONF5_MRP         (_ULCAST_(1) << 3)
 #define MIPS_CONF5_LLB         (_ULCAST_(1) << 4)
 #define MIPS_CONF5_MVH         (_ULCAST_(1) << 5)
+#define MIPS_CONF5_VP          (_ULCAST_(1) << 7)
 #define MIPS_CONF5_FRE         (_ULCAST_(1) << 8)
 #define MIPS_CONF5_UFE         (_ULCAST_(1) << 9)
 #define MIPS_CONF5_MSAEN       (_ULCAST_(1) << 27)
@@ -633,6 +638,8 @@
 #define MIPS_CONF6_SYND                (_ULCAST_(1) << 13)
 /* proAptiv FTLB on/off bit */
 #define MIPS_CONF6_FTLBEN      (_ULCAST_(1) << 15)
+/* Loongson-3 FTLB on/off bit */
+#define MIPS_CONF6_FTLBDIS     (_ULCAST_(1) << 22)
 /* FTLB probability bits */
 #define MIPS_CONF6_FTLBP_SHIFT (16)
 
@@ -645,12 +652,38 @@
 /* FTLB probability bits for R6 */
 #define MIPS_CONF7_FTLBP_SHIFT (18)
 
+/* WatchLo* register definitions */
+#define MIPS_WATCHLO_IRW       (_ULCAST_(0x7) << 0)
+
+/* WatchHi* register definitions */
+#define MIPS_WATCHHI_M         (_ULCAST_(1) << 31)
+#define MIPS_WATCHHI_G         (_ULCAST_(1) << 30)
+#define MIPS_WATCHHI_WM                (_ULCAST_(0x3) << 28)
+#define MIPS_WATCHHI_WM_R_RVA  (_ULCAST_(0) << 28)
+#define MIPS_WATCHHI_WM_R_GPA  (_ULCAST_(1) << 28)
+#define MIPS_WATCHHI_WM_G_GVA  (_ULCAST_(2) << 28)
+#define MIPS_WATCHHI_EAS       (_ULCAST_(0x3) << 24)
+#define MIPS_WATCHHI_ASID      (_ULCAST_(0xff) << 16)
+#define MIPS_WATCHHI_MASK      (_ULCAST_(0x1ff) << 3)
+#define MIPS_WATCHHI_I         (_ULCAST_(1) << 2)
+#define MIPS_WATCHHI_R         (_ULCAST_(1) << 1)
+#define MIPS_WATCHHI_W         (_ULCAST_(1) << 0)
+#define MIPS_WATCHHI_IRW       (_ULCAST_(0x7) << 0)
+
 /* MAAR bit definitions */
 #define MIPS_MAAR_ADDR         ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 #define MIPS_MAAR_ADDR_SHIFT   12
 #define MIPS_MAAR_S            (_ULCAST_(1) << 1)
 #define MIPS_MAAR_V            (_ULCAST_(1) << 0)
 
+/* EBase bit definitions */
+#define MIPS_EBASE_CPUNUM_SHIFT        0
+#define MIPS_EBASE_CPUNUM      (_ULCAST_(0x3ff) << 0)
+#define MIPS_EBASE_WG_SHIFT    11
+#define MIPS_EBASE_WG          (_ULCAST_(1) << 11)
+#define MIPS_EBASE_BASE_SHIFT  12
+#define MIPS_EBASE_BASE                (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
+
 /* CMGCRBase bit definitions */
 #define MIPS_CMGCRB_BASE       11
 #define MIPS_CMGCRF_BASE       (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
@@ -757,6 +790,15 @@
 /* Disable Branch Return Cache */
 #define R10K_DIAG_D_BRC                (_ULCAST_(1) << 22)
 
+/* Flush ITLB */
+#define LOONGSON_DIAG_ITLB     (_ULCAST_(1) << 2)
+/* Flush DTLB */
+#define LOONGSON_DIAG_DTLB     (_ULCAST_(1) << 3)
+/* Flush VTLB */
+#define LOONGSON_DIAG_VTLB     (_ULCAST_(1) << 12)
+/* Flush FTLB */
+#define LOONGSON_DIAG_FTLB     (_ULCAST_(1) << 13)
+
 /*
  * Coprocessor 1 (FPU) register names
  */
@@ -1442,6 +1484,12 @@ do {                                                                     \
 #define read_c0_pwctl()                __read_32bit_c0_register($6, 6)
 #define write_c0_pwctl(val)    __write_32bit_c0_register($6, 6, val)
 
+#define read_c0_pgd()          __read_64bit_c0_register($9, 7)
+#define write_c0_pgd(val)      __write_64bit_c0_register($9, 7, val)
+
+#define read_c0_kpgd()         __read_64bit_c0_register($31, 7)
+#define write_c0_kpgd(val)     __write_64bit_c0_register($31, 7, val)
+
 /* Cavium OCTEON (cnMIPS) */
 #define read_c0_cvmcount()     __read_ulong_c0_register($9, 6)
 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
@@ -2064,7 +2112,7 @@ __BUILD_SET_C0(brcm_mode)
  */
 static inline unsigned int get_ebase_cpunum(void)
 {
-       return read_c0_ebase() & 0x3ff;
+       return read_c0_ebase() & MIPS_EBASE_CPUNUM;
 }
 
 #endif /* !__ASSEMBLY__ */