update to 2015.04-rc1

[karo-tx-uboot.git] / arch / mips / lib / cache.c

diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/lib/cache.c
similarity index 55%
rename from arch/mips/cpu/mips32/cpu.c
rename to arch/mips/lib/cache.c
index 278865b6fff54849c98b0e1bd69a7cc7b2e5ba6f..e245614d1688e22cf325e2f8eaa4c79ca39a0fa3 100644 (file)
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/lib/cache.c
@@ -6,33 +6,8 @@
  */
 
 #include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/mipsregs.h>
 #include <asm/cacheops.h>
-#include <asm/reboot.h>
-
-#define cache_op(op,addr)                                              \
-       __asm__ __volatile__(                                           \
-       "       .set    push                                    \n"     \
-       "       .set    noreorder                               \n"     \
-       "       .set    mips3\n\t                               \n"     \
-       "       cache   %0, %1                                  \n"     \
-       "       .set    pop                                     \n"     \
-       :                                                               \
-       : "i" (op), "R" (*(unsigned char *)(addr)))
-
-void __attribute__((weak)) _machine_restart(void)
-{
-}
-
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-       _machine_restart();
-
-       fprintf(stderr, "*** reset failed ***\n");
-       return 0;
-}
+#include <asm/mipsregs.h>
 
 #ifdef CONFIG_SYS_CACHELINE_SIZE
 
@@ -74,20 +49,20 @@ void flush_cache(ulong start_addr, ulong size)
 {
        unsigned long ilsize = icache_line_size();
        unsigned long dlsize = dcache_line_size();
-       unsigned long addr, aend;
+       const void *addr, *aend;
 
        /* aend will be miscalculated when size is zero, so we return here */
        if (size == 0)
                return;
 
-       addr = start_addr & ~(dlsize - 1);
-       aend = (start_addr + size - 1) & ~(dlsize - 1);
+       addr = (const void *)(start_addr & ~(dlsize - 1));
+       aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
 
        if (ilsize == dlsize) {
                /* flush I-cache & D-cache simultaneously */
                while (1) {
-                       cache_op(HIT_WRITEBACK_INV_D, addr);
-                       cache_op(HIT_INVALIDATE_I, addr);
+                       mips_cache(HIT_WRITEBACK_INV_D, addr);
+                       mips_cache(HIT_INVALIDATE_I, addr);
                        if (addr == aend)
                                break;
                        addr += dlsize;
@@ -97,17 +72,17 @@ void flush_cache(ulong start_addr, ulong size)
 
        /* flush D-cache */
        while (1) {
-               cache_op(HIT_WRITEBACK_INV_D, addr);
+               mips_cache(HIT_WRITEBACK_INV_D, addr);
                if (addr == aend)
                        break;
                addr += dlsize;
        }
 
        /* flush I-cache */
-       addr = start_addr & ~(ilsize - 1);
-       aend = (start_addr + size - 1) & ~(ilsize - 1);
+       addr = (const void *)(start_addr & ~(ilsize - 1));
+       aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
        while (1) {
-               cache_op(HIT_INVALIDATE_I, addr);
+               mips_cache(HIT_INVALIDATE_I, addr);
                if (addr == aend)
                        break;
                addr += ilsize;
@@ -117,11 +92,11 @@ void flush_cache(ulong start_addr, ulong size)
 void flush_dcache_range(ulong start_addr, ulong stop)
 {
        unsigned long lsize = dcache_line_size();
-       unsigned long addr = start_addr & ~(lsize - 1);
-       unsigned long aend = (stop - 1) & ~(lsize - 1);
+       const void *addr = (const void *)(start_addr & ~(lsize - 1));
+       const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
        while (1) {
-               cache_op(HIT_WRITEBACK_INV_D, addr);
+               mips_cache(HIT_WRITEBACK_INV_D, addr);
                if (addr == aend)
                        break;
                addr += lsize;
@@ -131,31 +106,13 @@ void flush_dcache_range(ulong start_addr, ulong stop)
 void invalidate_dcache_range(ulong start_addr, ulong stop)
 {
        unsigned long lsize = dcache_line_size();
-       unsigned long addr = start_addr & ~(lsize - 1);
-       unsigned long aend = (stop - 1) & ~(lsize - 1);
+       const void *addr = (const void *)(start_addr & ~(lsize - 1));
+       const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
        while (1) {
-               cache_op(HIT_INVALIDATE_D, addr);
+               mips_cache(HIT_INVALIDATE_D, addr);
                if (addr == aend)
                        break;
                addr += lsize;
        }
 }
-
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
-       write_c0_entrylo0(low0);
-       write_c0_pagemask(pagemask);
-       write_c0_entrylo1(low1);
-       write_c0_entryhi(hi);
-       write_c0_index(index);
-       tlb_write_indexed();
-}
-
-int cpu_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_SOC_AU1X00
-       au1x00_enet_initialize(bis);
-#endif
-       return 0;
-}