#define kdebug(FMT, ...) do {} while (0)
#endif
-static int misalignment_addr(unsigned long *registers, unsigned params,
- unsigned opcode, unsigned long disp,
- void **_address, unsigned long **_postinc);
+static int misalignment_addr(unsigned long *registers, unsigned long sp,
+ unsigned params, unsigned opcode,
+ unsigned long disp,
+ void **_address, unsigned long **_postinc,
+ unsigned long *_inc);
static int misalignment_reg(unsigned long *registers, unsigned params,
unsigned opcode, unsigned long disp,
unsigned long **_register);
+static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode);
+
static const unsigned Dreg_index[] = {
REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
};
FMT_D7,
FMT_D8,
FMT_D9,
+ FMT_D10,
};
static const struct {
[FMT_D7] = { 24, 8 },
[FMT_D8] = { 24, 24 },
[FMT_D9] = { 24, 32 },
+ [FMT_D10] = { 32, 0 },
};
enum value_id {
};
struct mn10300_opcode {
- const char *name;
+ const char name[8];
u_int32_t opcode;
u_int32_t opmask;
unsigned exclusion;
{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
-{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}},
-{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}},
{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
{ "movhu", 0xfeda0000, 0xffff0f00, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, SP)}},
{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
-{ 0, 0, 0, 0, 0, 0, {0}},
+
+{ "mov_llt", 0xf7e00000, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+{ "mov_lgt", 0xf7e00001, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+{ "mov_lge", 0xf7e00002, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+{ "mov_lle", 0xf7e00003, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+{ "mov_lcs", 0xf7e00004, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+{ "mov_lhi", 0xf7e00005, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+{ "mov_lcc", 0xf7e00006, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+{ "mov_lls", 0xf7e00007, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+{ "mov_leq", 0xf7e00008, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+{ "mov_lne", 0xf7e00009, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+{ "mov_lra", 0xf7e0000a, 0xffff000f, 0x22, FMT_D10, AM33, {MEMINC2 (RN4,SIMM4_2), RM6}},
+
+{ "", 0, 0, 0, 0, 0, {0}},
};
/*
const struct exception_table_entry *fixup;
const struct mn10300_opcode *pop;
unsigned long *registers = (unsigned long *) regs;
- unsigned long data, *store, *postinc, disp;
+ unsigned long data, *store, *postinc, disp, inc, sp;
mm_segment_t seg;
siginfo_t info;
uint32_t opcode, noc, xo, xm;
- uint8_t *pc, byte;
+ uint8_t *pc, byte, datasz;
void *address;
unsigned tmp, npop, dispsz, loop;
- kdebug("==>misalignment({pc=%lx})", regs->pc);
+ /* we don't fix up userspace misalignment faults */
+ if (user_mode(regs))
+ goto bus_error;
+
+ sp = (unsigned long) regs + sizeof(*regs);
+
+ kdebug("==>misalignment({pc=%lx,sp=%lx})", regs->pc, sp);
if (regs->epsw & EPSW_IE)
asm volatile("or %0,epsw" : : "i"(EPSW_IE));
opcode = byte;
noc = 8;
- for (pop = mn10300_opcodes; pop->name; pop++) {
+ for (pop = mn10300_opcodes; pop->name[0]; pop++) {
npop = ilog2(pop->opcode | pop->opmask);
if (npop <= 0 || npop > 31)
continue;
}
/* didn't manage to find a fixup */
- if (!user_mode(regs))
- printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
- regs->pc, opcode);
+ printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
+ regs->pc, opcode);
failed:
set_fs(seg);
if (die_if_no_fixup("misalignment error", regs, code))
return;
+bus_error:
info.si_signo = SIGBUS;
info.si_errno = 0;
info.si_code = BUS_ADRALN;
/* error reading opcodes */
fetch_error:
- if (!user_mode(regs))
- printk(KERN_CRIT
- "MISALIGN: %p: fault whilst reading instruction data\n",
- pc);
+ printk(KERN_CRIT
+ "MISALIGN: %p: fault whilst reading instruction data\n",
+ pc);
goto failed;
bad_addr_mode:
- if (!user_mode(regs))
- printk(KERN_CRIT
- "MISALIGN: %lx: unsupported addressing mode %x\n",
- regs->pc, opcode);
+ printk(KERN_CRIT
+ "MISALIGN: %lx: unsupported addressing mode %x\n",
+ regs->pc, opcode);
goto failed;
bad_reg_mode:
- if (!user_mode(regs))
- printk(KERN_CRIT
- "MISALIGN: %lx: unsupported register mode %x\n",
- regs->pc, opcode);
+ printk(KERN_CRIT
+ "MISALIGN: %lx: unsupported register mode %x\n",
+ regs->pc, opcode);
goto failed;
unsupported_instruction:
- if (!user_mode(regs))
- printk(KERN_CRIT
- "MISALIGN: %lx: unsupported instruction %x (%s)\n",
- regs->pc, opcode, pop->name);
+ printk(KERN_CRIT
+ "MISALIGN: %lx: unsupported instruction %x (%s)\n",
+ regs->pc, opcode, pop->name);
goto failed;
transfer_failed:
kdebug("disp=%lx", disp);
set_fs(KERNEL_XDS);
- if (fixup || regs->epsw & EPSW_nSL)
+ if (fixup)
set_fs(seg);
tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
if (!tmp) {
- if (!user_mode(regs))
- printk(KERN_CRIT
- "MISALIGN: %lx:"
- " insn not move to/from memory %x\n",
- regs->pc, opcode);
+ printk(KERN_CRIT
+ "MISALIGN: %lx: insn not move to/from memory %x\n",
+ regs->pc, opcode);
goto failed;
}
+ /* determine the data transfer size of the move */
+ if (pop->name[3] == 0 || /* "mov" */
+ pop->name[4] == 'l') /* mov_lcc */
+ inc = datasz = 4;
+ else if (pop->name[3] == 'h') /* movhu */
+ inc = datasz = 2;
+ else
+ goto unsupported_instruction;
+
if (pop->params[0] & 0x80000000) {
/* move memory to register */
- if (!misalignment_addr(registers, pop->params[0], opcode, disp,
- &address, &postinc))
+ if (!misalignment_addr(registers, sp,
+ pop->params[0], opcode, disp,
+ &address, &postinc, &inc))
goto bad_addr_mode;
if (!misalignment_reg(registers, pop->params[1], opcode, disp,
&store))
goto bad_reg_mode;
- if (strcmp(pop->name, "mov") == 0) {
- kdebug("mov (%p),DARn", address);
- if (copy_from_user(&data, (void *) address, 4) != 0)
- goto transfer_failed;
- if (pop->params[0] & 0x1000000)
- *postinc += 4;
- } else if (strcmp(pop->name, "movhu") == 0) {
- kdebug("movhu (%p),DARn", address);
- data = 0;
- if (copy_from_user(&data, (void *) address, 2) != 0)
- goto transfer_failed;
- if (pop->params[0] & 0x1000000)
- *postinc += 2;
- } else {
- goto unsupported_instruction;
+ kdebug("mov%u (%p),DARn", datasz, address);
+ if (copy_from_user(&data, (void *) address, datasz) != 0)
+ goto transfer_failed;
+ if (pop->params[0] & 0x1000000) {
+ kdebug("inc=%lx", inc);
+ *postinc += inc;
}
*store = data;
+ kdebug("loaded %lx", data);
} else {
/* move register to memory */
if (!misalignment_reg(registers, pop->params[0], opcode, disp,
&store))
goto bad_reg_mode;
- if (!misalignment_addr(registers, pop->params[1], opcode, disp,
- &address, &postinc))
+ if (!misalignment_addr(registers, sp,
+ pop->params[1], opcode, disp,
+ &address, &postinc, &inc))
goto bad_addr_mode;
data = *store;
- if (strcmp(pop->name, "mov") == 0) {
- kdebug("mov %lx,(%p)", data, address);
- if (copy_to_user((void *) address, &data, 4) != 0)
- goto transfer_failed;
- if (pop->params[1] & 0x1000000)
- *postinc += 4;
- } else if (strcmp(pop->name, "movhu") == 0) {
- kdebug("movhu %hx,(%p)", (uint16_t) data, address);
- if (copy_to_user((void *) address, &data, 2) != 0)
- goto transfer_failed;
- if (pop->params[1] & 0x1000000)
- *postinc += 2;
- } else {
- goto unsupported_instruction;
- }
+ kdebug("mov%u %lx,(%p)", datasz, data, address);
+ if (copy_to_user((void *) address, &data, datasz) != 0)
+ goto transfer_failed;
+ if (pop->params[1] & 0x1000000)
+ *postinc += inc;
}
tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
regs->pc += tmp >> 3;
+ /* handle MOV_Lcc, which are currently the only FMT_D10 insns that
+ * access memory */
+ if (pop->format == FMT_D10)
+ misalignment_MOV_Lcc(regs, opcode);
+
set_fs(seg);
- return;
}
/*
* determine the address that was being accessed
*/
-static int misalignment_addr(unsigned long *registers, unsigned params,
- unsigned opcode, unsigned long disp,
- void **_address, unsigned long **_postinc)
+static int misalignment_addr(unsigned long *registers, unsigned long sp,
+ unsigned params, unsigned opcode,
+ unsigned long disp,
+ void **_address, unsigned long **_postinc,
+ unsigned long *_inc)
{
unsigned long *postinc = NULL, address = 0, tmp;
+ if (!(params & 0x1000000)) {
+ kdebug("noinc");
+ *_inc = 0;
+ _inc = NULL;
+ }
+
params &= 0x00ffffff;
do {
address += *postinc;
break;
case DM1:
- postinc = ®isters[Dreg_index[opcode >> 2 & 0x0c]];
+ postinc = ®isters[Dreg_index[opcode >> 2 & 0x03]];
address += *postinc;
break;
case DM2:
- postinc = ®isters[Dreg_index[opcode >> 4 & 0x30]];
+ postinc = ®isters[Dreg_index[opcode >> 4 & 0x03]];
address += *postinc;
break;
case AM0:
address += *postinc;
break;
case AM1:
- postinc = ®isters[Areg_index[opcode >> 2 & 0x0c]];
+ postinc = ®isters[Areg_index[opcode >> 2 & 0x03]];
address += *postinc;
break;
case AM2:
- postinc = ®isters[Areg_index[opcode >> 4 & 0x30]];
+ postinc = ®isters[Areg_index[opcode >> 4 & 0x03]];
address += *postinc;
break;
case RM0:
address += *postinc;
break;
case SP:
- address += registers[REG_SP >> 2];
+ address += sp;
break;
+ /* displacements are either to be added to the address
+ * before use, or, in the case of post-inc addressing,
+ * to be added into the base register after use */
case SD8:
case SIMM8:
- address += (int32_t) (int8_t) (disp & 0xff);
- break;
+ disp = (long) (int8_t) (disp & 0xff);
+ goto displace_or_inc;
case SD16:
- address += (int32_t) (int16_t) (disp & 0xffff);
- break;
+ disp = (long) (int16_t) (disp & 0xffff);
+ goto displace_or_inc;
case SD24:
tmp = disp << 8;
asm("asr 8,%0" : "=r"(tmp) : "0"(tmp));
- address += tmp;
- break;
+ disp = (long) tmp;
+ goto displace_or_inc;
case SIMM4_2:
tmp = opcode >> 4 & 0x0f;
tmp <<= 28;
asm("asr 28,%0" : "=r"(tmp) : "0"(tmp));
- address += tmp;
- break;
+ disp = (long) tmp;
+ goto displace_or_inc;
+ case IMM8:
+ disp &= 0x000000ff;
+ goto displace_or_inc;
+ case IMM16:
+ disp &= 0x0000ffff;
+ goto displace_or_inc;
case IMM24:
- address += disp & 0x00ffffff;
- break;
+ disp &= 0x00ffffff;
+ goto displace_or_inc;
case IMM32:
case IMM32_MEM:
case IMM32_HIGH8:
case IMM32_HIGH8_MEM:
- address += disp;
+ displace_or_inc:
+ kdebug("%s %lx", _inc ? "incr" : "disp", disp);
+ if (!_inc)
+ address += disp;
+ else
+ *_inc = disp;
break;
default:
BUG();
return 1;
}
+/*
+ * handle the conditional loop part of the move-and-loop instructions
+ */
+static void misalignment_MOV_Lcc(struct pt_regs *regs, uint32_t opcode)
+{
+ unsigned long epsw = regs->epsw;
+ unsigned long NxorV;
+
+ kdebug("MOV_Lcc %x [flags=%lx]", opcode, epsw & 0xf);
+
+ /* calculate N^V and shift onto the same bit position as Z */
+ NxorV = ((epsw >> 3) ^ epsw >> 1) & 1;
+
+ switch (opcode & 0xf) {
+ case 0x0: /* MOV_LLT: N^V */
+ if (NxorV)
+ goto take_the_loop;
+ return;
+ case 0x1: /* MOV_LGT: ~(Z or (N^V))*/
+ if (!((epsw & EPSW_FLAG_Z) | NxorV))
+ goto take_the_loop;
+ return;
+ case 0x2: /* MOV_LGE: ~(N^V) */
+ if (!NxorV)
+ goto take_the_loop;
+ return;
+ case 0x3: /* MOV_LLE: Z or (N^V) */
+ if ((epsw & EPSW_FLAG_Z) | NxorV)
+ goto take_the_loop;
+ return;
+
+ case 0x4: /* MOV_LCS: C */
+ if (epsw & EPSW_FLAG_C)
+ goto take_the_loop;
+ return;
+ case 0x5: /* MOV_LHI: ~(C or Z) */
+ if (!(epsw & (EPSW_FLAG_C | EPSW_FLAG_Z)))
+ goto take_the_loop;
+ return;
+ case 0x6: /* MOV_LCC: ~C */
+ if (!(epsw & EPSW_FLAG_C))
+ goto take_the_loop;
+ return;
+ case 0x7: /* MOV_LLS: C or Z */
+ if (epsw & (EPSW_FLAG_C | EPSW_FLAG_Z))
+ goto take_the_loop;
+ return;
+
+ case 0x8: /* MOV_LEQ: Z */
+ if (epsw & EPSW_FLAG_Z)
+ goto take_the_loop;
+ return;
+ case 0x9: /* MOV_LNE: ~Z */
+ if (!(epsw & EPSW_FLAG_Z))
+ goto take_the_loop;
+ return;
+ case 0xa: /* MOV_LRA: always */
+ goto take_the_loop;
+
+ default:
+ BUG();
+ }
+
+take_the_loop:
+ /* wind the PC back to just after the SETLB insn */
+ kdebug("loop LAR=%lx", regs->lar);
+ regs->pc = regs->lar - 4;
+}
+
/*
* misalignment handler tests
*/
projects / mv-sheeva.git / blobdiff