/ {
model = "fsl,lite5200";
// revision = "1.0";
- compatible = "fsl,lite5200\0generic-mpc5200";
+ compatible = "fsl,lite5200";
#address-cells = <1>;
#size-cells = <1>;
timebase-frequency = <0>; // from bootloader
bus-frequency = <0>; // from bootloader
clock-frequency = <0>; // from bootloader
- 32-bit;
};
};
soc5200@f0000000 {
model = "fsl,mpc5200";
compatible = "mpc5200";
- revision = "" // from bootloader
- #interrupt-cells = <3>;
+ revision = ""; // from bootloader
device_type = "soc";
- ranges = <0 f0000000 f0010000>;
- reg = <f0000000 00010000>;
+ ranges = <0 f0000000 0000c000>;
+ reg = <f0000000 00000100>;
bus-frequency = <0>; // from bootloader
system-frequency = <0>; // from bootloader
reg = <200 38>;
};
- pic@500 {
+ mpc5200_pic: pic@500 {
// 5200 interrupts are encoded into two levels;
- linux,phandle = <500>;
interrupt-controller;
#interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "mpc5200-pic";
reg = <500 80>;
- built-in;
};
gpt@600 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <0>;
reg = <600 10>;
interrupts = <1 9 0>;
- interrupt-parent = <500>;
- has-wdt;
+ interrupt-parent = <&mpc5200_pic>;
+ fsl,has-wdt;
};
gpt@610 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <1>;
reg = <610 10>;
interrupts = <1 a 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
gpt@620 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <2>;
reg = <620 10>;
interrupts = <1 b 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
gpt@630 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <3>;
reg = <630 10>;
interrupts = <1 c 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
gpt@640 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <4>;
reg = <640 10>;
interrupts = <1 d 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
gpt@650 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <5>;
reg = <650 10>;
interrupts = <1 e 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
gpt@660 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <6>;
reg = <660 10>;
interrupts = <1 f 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
gpt@670 { // General Purpose Timer
- compatible = "mpc5200-gpt";
- device_type = "gpt";
+ compatible = "fsl,mpc5200-gpt";
cell-index = <7>;
reg = <670 10>;
interrupts = <1 10 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
rtc@800 { // Real time clock
device_type = "rtc";
reg = <800 100>;
interrupts = <1 5 0 1 6 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
mscan@900 {
compatible = "mpc5200-mscan";
cell-index = <0>;
interrupts = <2 11 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
reg = <900 80>;
};
compatible = "mpc5200-mscan";
cell-index = <1>;
interrupts = <2 12 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
reg = <980 80>;
};
compatible = "mpc5200-gpio";
reg = <b00 40>;
interrupts = <1 7 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
gpio-wkup@c00 {
compatible = "mpc5200-gpio-wkup";
reg = <c00 40>;
interrupts = <1 8 0 0 3 0>;
- interrupt-parent = <500>;
- };
-
- pci@0d00 {
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- compatible = "mpc5200-pci";
- reg = <d00 100>;
- interrupt-map-mask = <f800 0 0 7>;
- interrupt-map = <c000 0 0 1 500 0 0 3
- c000 0 0 2 500 0 0 3
- c000 0 0 3 500 0 0 3
- c000 0 0 4 500 0 0 3>;
- clock-frequency = <0>; // From boot loader
- interrupts = <2 8 0 2 9 0 2 a 0>;
- interrupt-parent = <500>;
- bus-range = <0 0>;
- ranges = <42000000 0 80000000 80000000 0 20000000
- 02000000 0 a0000000 a0000000 0 10000000
- 01000000 0 00000000 b0000000 0 01000000>;
+ interrupt-parent = <&mpc5200_pic>;
};
spi@f00 {
compatible = "mpc5200-spi";
reg = <f00 20>;
interrupts = <2 d 0 2 e 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
usb@1000 {
device_type = "usb-ohci-be";
- compatible = "mpc5200-ohci\0ohci-be";
+ compatible = "mpc5200-ohci","ohci-be";
reg = <1000 ff>;
interrupts = <2 6 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
bestcomm@1200 {
3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 a 0 3 b 0
3 c 0 3 d 0 3 e 0 3 f 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
xlb@1f00 {
cell-index = <0>;
reg = <2000 100>;
interrupts = <2 1 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
// PSC2 in ac97 mode example
// cell-index = <1>;
// reg = <2200 100>;
// interrupts = <2 2 0>;
- // interrupt-parent = <500>;
+ // interrupt-parent = <&mpc5200_pic>;
//};
// PSC3 in CODEC mode example
// cell-index = <2>;
// reg = <2400 100>;
// interrupts = <2 3 0>;
- // interrupt-parent = <500>;
+ // interrupt-parent = <&mpc5200_pic>;
//};
// PSC4 in uart mode example
// cell-index = <3>;
// reg = <2600 100>;
// interrupts = <2 b 0>;
- // interrupt-parent = <500>;
+ // interrupt-parent = <&mpc5200_pic>;
//};
// PSC5 in uart mode example
// cell-index = <4>;
// reg = <2800 100>;
// interrupts = <2 c 0>;
- // interrupt-parent = <500>;
+ // interrupt-parent = <&mpc5200_pic>;
//};
// PSC6 in spi mode example
// cell-index = <5>;
// reg = <2c00 100>;
// interrupts = <2 4 0>;
- // interrupt-parent = <500>;
+ // interrupt-parent = <&mpc5200_pic>;
//};
ethernet@3000 {
reg = <3000 800>;
mac-address = [ 02 03 04 05 06 07 ]; // Bad!
interrupts = <2 5 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
ata@3a00 {
compatible = "mpc5200-ata";
reg = <3a00 100>;
interrupts = <2 7 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
};
i2c@3d00 {
- device_type = "i2c";
- compatible = "mpc5200-i2c\0fsl-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <3d00 40>;
interrupts = <2 f 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
i2c@3d40 {
- device_type = "i2c";
- compatible = "mpc5200-i2c\0fsl-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <3d40 40>;
interrupts = <2 10 0>;
- interrupt-parent = <500>;
+ interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking;
};
sram@8000 {
device_type = "sram";
- compatible = "mpc5200-sram\0sram";
+ compatible = "mpc5200-sram","sram";
reg = <8000 4000>;
};
};
+
+ pci@f0000d00 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ compatible = "mpc5200-pci";
+ reg = <f0000d00 100>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
+ c000 0 0 2 &mpc5200_pic 0 0 3
+ c000 0 0 3 &mpc5200_pic 0 0 3
+ c000 0 0 4 &mpc5200_pic 0 0 3>;
+ clock-frequency = <0>; // From boot loader
+ interrupts = <2 8 0 2 9 0 2 a 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ bus-range = <0 0>;
+ ranges = <42000000 0 80000000 80000000 0 20000000
+ 02000000 0 a0000000 a0000000 0 10000000
+ 01000000 0 00000000 b0000000 0 01000000>;
+ };
};