powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 97a7fe1b9792532aa9f35b98ce898487966c5bc8..f293265c860db62c688b2132bea82784d3bdcfe5 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -38,6 +38,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
+#include <hwconfig.h>
 #include <linux/compiler.h>
 #include "mp.h"
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
@@ -47,6 +48,8 @@
 
 #include "../../../../drivers/block/fsl_sata.h"
 
+#define HWCONFIG_BUFFER_SIZE 128
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_QE
@@ -308,10 +311,48 @@ int cpu_init_r(void)
        volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
 #endif
 
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
-       flush_dcache();
-       mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
-       sync();
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+       defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+       /*
+        * CPU22 and NMG_CPU_A011 share the same workaround.
+        * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+        * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+        * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
+        * fixed in 2.0. NMG_CPU_A011 is activated by default and can
+        * be disabled by hwconfig with syntax:
+        *
+        * fsl_cpu_a011:disable
+        */
+       extern int enable_cpu_a011_workaround;
+#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
+       enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
+#else
+       char buffer[HWCONFIG_BUFFER_SIZE];
+       char *buf = NULL;
+       int n, res;
+
+       n = getenv_f("hwconfig", buffer, sizeof(buffer));
+       if (n > 0)
+               buf = buffer;
+
+       res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
+       if (res > 0)
+               enable_cpu_a011_workaround = 0;
+       else {
+               if (n >= HWCONFIG_BUFFER_SIZE) {
+                       printf("fsl_cpu_a011 was not found. hwconfig variable "
+                               "may be too long\n");
+               }
+               enable_cpu_a011_workaround =
+                       (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
+                       (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
+       }
+#endif
+       if (enable_cpu_a011_workaround) {
+               flush_dcache();
+               mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
+               sync();
+       }
 #endif
 
        puts ("L2:    ");
@@ -354,8 +395,7 @@ int cpu_init_r(void)
                break;
        case 0x1:
                if (ver == SVR_8540 || ver == SVR_8560   ||
-                   ver == SVR_8541 || ver == SVR_8541_E ||
-                   ver == SVR_8555 || ver == SVR_8555_E) {
+                   ver == SVR_8541 || ver == SVR_8555) {
                        puts("128 KB ");
                        /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
                        cache_ctl = 0xc4000000;
@@ -366,8 +406,7 @@ int cpu_init_r(void)
                break;
        case 0x2:
                if (ver == SVR_8540 || ver == SVR_8560   ||
-                   ver == SVR_8541 || ver == SVR_8541_E ||
-                   ver == SVR_8555 || ver == SVR_8555_E) {
+                   ver == SVR_8541 || ver == SVR_8555) {
                        puts("256 KB ");
                        /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
                        cache_ctl = 0xc8000000;
@@ -403,8 +442,7 @@ int cpu_init_r(void)
                puts("enabled\n");
        }
 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
-       if ((SVR_SOC_VER(svr) == SVR_P2040) ||
-           (SVR_SOC_VER(svr) == SVR_P2040_E)) {
+       if (SVR_SOC_VER(svr) == SVR_P2040) {
                puts("N/A\n");
                goto skip_l2;
        }
@@ -442,8 +480,18 @@ skip_l2:
 
 #ifdef CONFIG_SYS_SRIO
        srio_init();
-#ifdef CONFIG_SRIOBOOT_MASTER
-       srio_boot_master();
+#ifdef CONFIG_FSL_CORENET
+       char *s = getenv("bootmaster");
+       if (s) {
+               if (!strcmp(s, "SRIO1")) {
+                       srio_boot_master(1);
+                       srio_boot_master_release_slave(1);
+               }
+               if (!strcmp(s, "SRIO2")) {
+                       srio_boot_master(2);
+                       srio_boot_master_release_slave(2);
+               }
+       }
 #endif
 #endif
 
@@ -503,9 +551,7 @@ skip_l2:
         */
        if (IS_SVR_REV(svr, 1, 0) &&
            ((SVR_SOC_VER(svr) == SVR_P1022) ||
-            (SVR_SOC_VER(svr) == SVR_P1022_E) ||
-            (SVR_SOC_VER(svr) == SVR_P1013) ||
-            (SVR_SOC_VER(svr) == SVR_P1013_E))) {
+            (SVR_SOC_VER(svr) == SVR_P1013))) {
                fsl_sata_reg_t *reg;
 
                /* first SATA controller */
@@ -534,7 +580,7 @@ void arch_preboot_os(void)
         * disabled by the time we get called.
         */
        msr = mfmsr();
-       msr &= ~(MSR_ME|MSR_CE|MSR_DE);
+       msr &= ~(MSR_ME|MSR_CE);
        mtmsr(msr);
 
        setup_ivors();